文件列表:

Makefile (1812, 2023-03-30)
benchmark (0, 2023-03-30)
benchmark\Makefile (1203, 2023-03-30)
benchmark\benchmark.sdc (1230, 2023-03-30)
benchmark\div_bench.vhd (3194, 2023-03-30)
benchmark\fpu_bench.vhd (3952, 2023-03-30)
benchmark\mul32_bench.vhd (2224, 2023-03-30)
make_png.sh (337, 2023-03-30)
misc (0, 2023-03-30)
misc\mrisc32.sdc (425, 2023-03-30)
mrisc32-a1-pipeline.png (78418, 2023-03-30)
mrisc32-a1-pipeline.svg (143045, 2023-03-30)
out (0, 2023-03-30)
rtl (0, 2023-03-30)
rtl\Makefile (1360, 2023-03-30)
rtl\agu (0, 2023-03-30)
rtl\agu\Makefile (1184, 2023-03-30)
rtl\agu\agu.vhd (2885, 2023-03-30)
rtl\agu\vector_stride_gen.vhd (2666, 2023-03-30)
rtl\alu (0, 2023-03-30)
rtl\alu\Makefile (1517, 2023-03-30)
rtl\alu\add32.vhd (3743, 2023-03-30)
rtl\alu\alu.vhd (9561, 2023-03-30)
rtl\alu\clz32.vhd (6979, 2023-03-30)
rtl\alu\cmp32.vhd (7183, 2023-03-30)
rtl\alu\crc32.vhd (26630, 2023-03-30)
rtl\alu\crc32c.vhd (31263, 2023-03-30)
rtl\alu\pack32.vhd (6856, 2023-03-30)
rtl\alu\popcnt32.vhd (4595, 2023-03-30)
rtl\alu\rev32.vhd (2490, 2023-03-30)
rtl\alu\sel32.vhd (2272, 2023-03-30)
rtl\alu\shift32.vhd (11309, 2023-03-30)
rtl\alu\shuf32.vhd (3698, 2023-03-30)
rtl\alu\sub32.vhd (3749, 2023-03-30)
rtl\alu\xchgsr.vhd (2634, 2023-03-30)
... ...

# MRISC32-A1 This is a [VHDL](https://en.wikipedia.org/wiki/VHDL) implementation of a single issue, in-order CPU that implements the [MRISC32](https://github.com/mrisc32/mrisc32) ISA. The working name for the CPU is *MRISC32-A1*. ## Overview  ## Progress The CPU is nearing completion but still under development. The following components have been implemented: * A 9-stage pipeline. - PC and branching logic. - Instruction fetch. - Decode. - Register fetch. - Execute. - Data read/write logic (scalar and vector). - Register write-back. - Operand forwarding. * The integer ALU. - Supports all packed and unpacked integer ALU operations. - All ALU operations finish in one cycle. * A pipelined (three-cycle) integer multiply unit. - Supports all packed and unpacked integer multiplication operations. * A semi-pipelined integer and floating point division unit. - The integer division pipeline is 3 stages long, while the floating point division pipeline is 4 stages long. - 32-bit division: 15/12 cycles stall (integer/float). - 2 x 16-bit division: 7/5 cycles stall (integer/float). - 4 x 8-bit division: 3/2 cycles stall (integer/float). * A pipelined (two-cycle) Saturating Arithmetic Unit (SAU). - Supports all packed and unpacked saturating and halving arithmetic instructions. * An IEEE 754 compliant(ish) FPU. - The following single-cycle FPU instructions are implemented: - FMIN, FMAX - FSEQ, FSNE, FSLT, FSLE, FSUNORD, FSORD - The following three-cycle FPU instructions are implemented: - ITOF, UTOF, FTOI, FTOU, FTOIR, FTOUR - The following four-cycle FPU instructions are implemented: - FADD, FSUB, FMUL - Both packed and unpacked FPU operations are implemented. * The scalar register file. - There are three read ports and one write port. * The vector register file. - There are two read ports and one write port. - Each vector register has 16 elements (configurable). * An address generation unit (AGU). - The AGU supports all addressing modes. * Branch prediction and correction. - A direct mapped 2-bit dynamic branch predictor (512 entries, configurable). - A return address stack predictor (16 entries, configurable). - The branch misprediction penalty is 3 cycles (a correctly predicted branch incurs no penalty). * A direct mapped instruction cache. * Two 32-bit Wishbone (B4 pipelined) interfaces to the memory. - Instruction and data requests have separate Wishbone interfaces. - One memory request can be completed every cycle per interface. **TODO**: Data cache, interrupt logic. ## Configurability The aim is for the MRISC32-A1 to implement the complete MRISC32 ISA, which means that it is a fairly large design (including an FPU, hardware multiplication and division, packed operations, etc). If the design is too large or complex for a certain target chip (FPGA), it is possible to disable many features via `T_CORE_CONFIG` (see [config.vhd](rtl/common/config.vhd)). E.g. setting `HAS_MUL` to `false` will disable support for hardware multiplication. It is also possible to change the vector register size by chaging the value of `C_LOG2_VEC_REG_ELEMENTS` (4 means 16 elements, 5 means 32 elements, 8 means 256 elements, and so on). ## Performance The MRISC32-A1 can issue **one operation per clock cycle**. When synthesized against an [Intel Cyclone V FPGA](https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html), the maximum running frequency is close to **100 MHz**.

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