文件列表:

AXI4-Lite Bridge Verilog (0, 2023-04-29)
AXI4-Lite Bridge Verilog\AnleitungzurIPIntegration.pdf (3515308, 2023-04-29)
AXI4-Lite Bridge Verilog\AxiCan_Zustands.v (5566, 2023-04-29)
Documentation_Canakari.pdf (2797711, 2023-04-29)
LICENSE (1056, 2023-04-29)
Testbench (0, 2023-04-29)
Testbench\can_pattern_gen_pkg.vhd (3172, 2023-04-29)
Testbench\can_pattern_gen_pkg_body.vhd (14061, 2023-04-29)
Testbench\config_pkg.vhd (10702, 2023-04-29)
Testbench\config_pkg_body.vhd (20699, 2023-04-29)
Testbench\testbench.vhd (17190, 2023-04-29)
Verilog triplicated (0, 2023-04-29)
Verilog triplicated\accmaskreg2.v (1647, 2023-04-29)
Verilog triplicated\biterrordetect2.v (1977, 2023-04-29)
Verilog triplicated\bittime2.v (8222, 2023-04-29)
Verilog triplicated\bittiming2.v (7087, 2023-04-29)
Verilog triplicated\can2.v (12095, 2023-04-29)
Verilog triplicated\counter2.v (3687, 2023-04-29)
Verilog triplicated\decapsulation2.v (1909, 2023-04-29)
Verilog triplicated\destuffing2.v (4792, 2023-04-29)
Verilog triplicated\edgepuffer2.v (1957, 2023-04-29)
Verilog triplicated\encapsulation2.v (3155, 2023-04-29)
Verilog triplicated\equal_id2.v (2006, 2023-04-29)
Verilog triplicated\erbcount2.v (2619, 2023-04-29)
Verilog triplicated\fastshift2.v (3772, 2023-04-29)
Verilog triplicated\faultfsm2.v (4596, 2023-04-29)
Verilog triplicated\fce2.v (4383, 2023-04-29)
Verilog triplicated\fsm_register2.v (6562, 2023-04-29)
Verilog triplicated\generalregister2.v (2628, 2023-04-29)
Verilog triplicated\interruptregister2.v (2916, 2023-04-29)
Verilog triplicated\interruptunit2.v (5599, 2023-04-29)
Verilog triplicated\iocpuavalon2.v (20517, 2023-04-29)
Verilog triplicated\llc2.v (4882, 2023-04-29)
Verilog triplicated\llc_fsm2.v (14157, 2023-04-29)
Verilog triplicated\mac2.v (19322, 2023-04-29)
Verilog triplicated\macfsm2.v (207348, 2023-04-29)
Verilog triplicated\meslencompare2.v (4504, 2023-04-29)
... ...

# CANakari CAN-Controller The CANakari Controller was developed in the year 2000 as a part of a diploma thesis at [TH-Koln](https://www.th-koeln.de/startseite_16.php). CANakari is a CAN 2.0B Controller implementation in VHDL and Verilog. Over the years, various modifications and functional extensions have been done by students from [FH-Dortmund](https://www.fh-dortmund.de/de/fb/3/index.php) and [TH-Koln](https://www.th-koeln.de/startseite_16.php). By now, three different versions of the CANakari Controller do exist: * [VHDL Implementation](../main/Vhdl) * [Verilog Implementation](../main/Verilog) * [Verilog Implementation, triplicated](../main/Verilog%20triplicated) More detailed Information can be found in the [CANakari Documentation](../main/Documentation_Canakari.pdf). Der CANakari Controller wurde im Jahr 2000 im Rahmen einer Diplomarbeit an der [TH-Koln](https://www.th-koeln.de/startseite_16.php) entwickelt. Es handelt sich hierbei um eine CAN 2.0B Controller Implementierung in VHDL und Verilog. Uber die Jahre hinweg wurden von diversen Studenten der [FH-Dortmund](https://www.fh-dortmund.de/de/fb/3/index.php) und [TH-Koln](https://www.th-koeln.de/startseite_16.php) verschiedene Modifikationen vorgenommen und die Funktionalitat erweitert. Mittlerweile existieren drei verschiedene Versionen des CANakari Controllers: * [VHDL Implementierung](../main/Vhdl) * [Verilog Implementierung](../main/Verilog) * [Verilog Implementierung, tripliziert](../main/Verilog%20triplicated) Weitere Informationen konnen der [CANakari Dokumentation](../main/Documentation_Canakari.pdf) entnommen werden.

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：