fpga-iic-hygro-tester-1
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：70588KB
下载次数：0
上传日期：2023-04-30 23:15:38
上 传 者：
sh-1993
说明： 用于测试IIC传感器的温度和相对湿度读数的不同实现方式的小型FPGA项目
(A small FPGA project of different implementations for testing Temperature and Relative Humidity readings of a IIC sensor)
文件列表:
HYGRO Sensor Readings Tester.pdf (5817734, 2023-05-01)
HYGRO-Tester-Design-AXI (0, 2023-05-01)
HYGRO-Tester-Design-AXI\Constraints (0, 2023-05-01)
HYGRO-Tester-Design-AXI\Constraints\Arty-A7-100-Master.xdc (21431, 2023-05-01)
HYGRO-Tester-Design-AXI\IP (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0 (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\bd (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\bd\bd.tcl (7749, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\component.xml (69016, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0 (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\data (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\data\MuxSSD.mdd (173, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\data\MuxSSD.tcl (163, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\src (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\src\Makefile (449, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\src\MuxSSD.c (179, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\src\MuxSSD.h (2366, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\drivers\MuxSSD_v1_0\src\MuxSSD_selftest.c (1929, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs\bfm_design (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs\bfm_design\MuxSSD_v1_0_tb.sv (8589, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs\bfm_design\design.tcl (3692, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs\debug_hw_design (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs\debug_hw_design\MuxSSD_v1_0_hw_test.tcl (1351, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\example_designs\debug_hw_design\design.tcl (5670, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\hdl (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\hdl\MuxSSD_v1_0.vhd (6840, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\hdl\MuxSSD_v1_0_S00_AXI.vhd (15441, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\xgui (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\local_ip\MuxSSD_1.0\xgui\MuxSSD_v1_0.tcl (3494, 2023-05-01)
HYGRO-Tester-Design-AXI\IP\vivado-library (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IPI-BDs (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IPI-BDs\system_100 (0, 2023-05-01)
HYGRO-Tester-Design-AXI\IPI-BDs\system_100\hdl (0, 2023-05-01)
... ...
# fpga-iic-hygro-tester-1
FPGA IIC HYGRO Tester Version 1
by Timothy Stotts
Note that this project is deprecated. The most recent project, with wider
hardware support and occasional updates, is Version 3 and is located at:
[fpga-iic-hygro-tester-3](https://github.com/timothystotts/fpga-iic-hygro-tester-3)
## Description
A small FPGA project of different implementations for testing Temperature and Relative Humidity
readings of a I2C sensor.
The design targets the Digilent Inc. Arty-A7-100T FPGA development board containing a Xilinx Artix-7 FPGA.
Three peripherals are used: Digilent Inc. Pmod HYGRO, Digilent Inc. Pmod CLS., Digilent Inc. Pmod SSD.
The design is broken into two groupings.
The folder HYGRO-Tester-Design-AXI contains a Xilinx Vivado IP Integrator plus
Xilinx SDK design. A Microblaze soft CPU is instantiated to talk with board components,
a temperature and relative humidity sensor,
a 16x2 character LCD peripheral,
and a two-digit Seven Segment Display.
A Xilinx SDK project contains a very small Standalone program in C; drivers
for the peripherals, a main loop to operate and poll the sensor,
poll the switches and buttons,
update LCD, update 7SD, and color-mix RGB LEDs.
The folder HYGRO-Tester-Design-Verilog contains a Xilinx Vivado project with sources
containing only Verilog-2001 modules. Plain HDL without a soft CPU or C code is authored to
talk with board components,
a temperature and relative humidity sensor peripheral,
a 16x2 character LCD peripheral,
and a 2-digit 7-segment display.
These two groupings of design provide equivalent functionality, excepting that the HDL designs provide
additional animation effect of the board's three-emitter RGB LEDs. Both designs are in a prerelease
state and can be cloned or downloaded with the tag Hygro_Tester_Both_Prerelease_1A.
### Naming conventions notice
The Pmod CLS peripheral used in this project connects via a standard bus technology design called SPI.
The use of MOSI/MISO terminology is considered obsolete. COPI/CIPO is now used. The MOSI signal on a
controller can be replaced with the title 'COPI'. Master and Slave terms are now Controller and Peripheral.
Additional information can be found [here](https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names).
The choice to use COPI and CIPO instead of SDO and SDI for single-direction bus signals is simple.
On a single peripheral bus with two data lines of fixed direction, the usage of the signal name
"SDO" is dependent on whether the Controller or the Peripheral is the chip being discussed;
whereas COPI gives the exact direction regardless of which chip is being discussed. The author
of this website agrees with the open source community that the removal of offensive language from
standard terminology in engineering is a priority.
### Project information document:
```
./HYGRO Sensor Readings Tester.pdf
```
[HYGRO Sensor Readings Tester info](https://github.com/timothystotts/fpga-iic-hygro-tester-1/blob/main/HYGRO%20Sensor%20Readings%20Tester.pdf)
### Diagrams design document:
```
./HYGRO-Tester-Design-Documents/HYGRO-Tester-Design-Diagrams.pdf
```
[HYGRO Tester Design Diagrams info](https://github.com/timothystotts/fpga-iic-hygro-tester-1/blob/main/HYGRO-Tester-Design-Documents/HYGRO-Tester-Design-Diagrams.pdf)
#### Target device assembly: Arty-A7-100T with Pmod HYGRO on test header, Pmod CLS on extension cable, Pmod SSD on extension cable
#### Target device execution: Arty-A7-100T with Pmod HYGRO on test header, Pmod CLS on extension cable, Pmod SSD on extension cable
#### Block diagram architecture of the HDL designs:
#### Top Port diagram architecture of the HDL designs:
#### LCD FSM diagram of the HDL designs:
#### UART Feed FSM diagram of the HDL designs:
#### UART TX ONLY FSM diagram of the HDL designs:
#### 4-input Multi-Debouncer for 4 exclusve inputs, such as switches or buttons, of the HDL designs:
#### HYGRO Custom Driver Ports diagram of the HDL designs:
#### Pmod HYGRO IIC custom driver FSM for operating as a single setup and then poll once per second:
#### CLS Custom Driver Ports diagram of the HDL designs:
#### Generic Standard SPI Single Chip protocol bus driver, used by the ACL2 driver and the CLS driver
#### Pmod CLS Standard SPI custom driver FSM for operating the standard SPI driver to send text line refreshes to the ATmega48 microcontroller chip of the Pmod CLS:
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