文件列表:

LICENSE (1074, 2023-06-22)
Makefile (3551, 2023-06-22)
example (0, 2023-06-22)
example\runme.sh (195, 2023-06-22)
template (0, 2023-06-22)
template\Makefile (680, 2023-06-22)
template\bd (0, 2023-06-22)
template\build_project.tcl (25102, 2023-06-22)
template\constr (0, 2023-06-22)
template\constr\clocks.xdc (76, 2023-06-22)
template\constr\pins.xdc (277, 2023-06-22)
template\core (0, 2023-06-22)
template\rtl (0, 2023-06-22)
template\rtl\top.sv (449, 2023-06-22)
template\sim (0, 2023-06-22)
utils (0, 2023-06-22)
utils\vivado_export_xsa.tcl (199, 2023-06-22)
utils\vivado_impl.tcl (502, 2023-06-22)
utils\vivado_save_project.tcl (218, 2023-06-22)
utils\vivado_synth.tcl (470, 2023-06-22)
utils\vivado_timing.tcl (419, 2023-06-22)

# make-FPGA Set of scripts for handling Vivado's project in non-project mode. ## Just show me the code! Example project creating: ``` git clone https://github.com/vborchsh/make-fpga cd make-fpga/example source runme.sh ``` Now, you are in the `example_repo` folder with everything needed inside. And you can do: ``` make # This will give you some details make all # And this will build everything ``` ## Details ### Help First, let's ask for some help: ``` $ make help make-fpga is set of scripts for handling Vivado's non-project mode design flow Available options: BUILD_NAME?=build - project name; BUILD_PATH?=BUILD_NAME - project path (folder with BUILD_NAME.* subfolders); BUILD_ARCH?=zynq - architecture (zynq, zynqmp, fpga). Applicable only for 'bin' target. BUILD_JOBS?=16 - Number of threads for Vivado. Applicable only for 'synth' and 'impl' target. Available targets: all Creates project, run synthesys, implementation and exports xsa and bin files; bin Converts .bin file to the .bit.bin and copy it to the project's root. BUILD_ARCH should be checked!; build Run synthesys and implementation; clean Delete everything; create Creates Vivado's project BUILD_NAME in the BUILD_PATH directory; help Print this help. impl Open and run implementation for BUILD_NAME project. The project must be synthesized by "synth" target; open Open Vivado's project BUILD_NAME in the BUILD_PATH directory in GUI mode. Project must be created by "create" target save Open Vivado's project and save all settings to the build_project.tcl file by calling write_project_tcl; synth Open and run synthesis for BUILD_NAME project. The project must be created by "create" target; template Generates template project's structure with folders and gitignore; timing Check timing, return 1 in case slacks < 0; xsa Export .xsa file to the project's root; ``` ### Project from scratch You can run `template` target in empty folder and script will build repository's structure with files from `template` folder. The repository is created with a structure from the article: https://habr.com/ru/post/683580/. But you can modify these files to align to your needs. ### Existing project Also, you can save existing project to `build_project.tcl` and align for these scripts: ``` mkdir workspace && cd workspace git clone https://github.com/vborchsh/make-fpga cp make-fpga/template/Makefile . cp -r . make save BUILD_NAME= BUILD_PATH= ``` Example: ``` BUILD_NAME=top.xpr BUILD_PATH=top_prj path to project file: ./top_prj/top.xpr ``` But I preffer keep them the same: BUILD_PATH==BUILD_NAME. ### Project deploy ``` git clone --recursive cd make all ``` ### Project updating In case any changes in the project's structure and/or parameters (fileset, paths, compilation settings and so on) you have to run before commit: ``` make save ``` ## Errata Supports only bash, because of `extglob` using.

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：