文件列表:

CODE_OF_CONDUCT.md (5230, 2023-05-29)
ClockDivider.v (795, 2023-05-29)
Constraints.v (7395, 2023-05-29)
LICENSE.md (35149, 2023-05-29)
Learn (0, 2023-05-29)
Learn\LEARN.md (119, 2023-05-29)
TopModule.v (8184, 2023-05-29)
build (0, 2023-05-29)
build\TopModuleTB.v (2584, 2023-05-29)
build\sh (478, 2023-05-29)
build\testerFile.v (758, 2023-05-29)
writeups (0, 2023-05-29)
writeups\446 Group Project Presentation.pdf (1061879, 2023-05-29)
writeups\446 Report (1).pdf (1316119, 2023-05-29)
writeups\test.txt (1, 2023-05-29)

# Score-Board-FPGA-Verilog:     # Meet the team: This project was completed in EGCP 446 Fall 2022 by [Duy](https://github.com/duy301199), [Jeremy](https://github.com/jge162) and [Spencer](https://github.com/5pencerW). Spencer contributed the module used to keep team scores, I contributed by creating the countdown timer. Lastly, Duy setup the 7 segment! # Initial setup: Install [Xilinx Vivado](https://www.xilinx.com/products/design-tools/vivado.html) # Download zip folder: Open vivado and import project to IDE # Connect FPGA board: Make sure to select correct [FPGA board](https://digilent.com/shop/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/), Nexy's A7 # Create Bitstream: Once created you can then load program unto board and test software running. # Screen shot of FPGA board: # License info: Copyright (c) 2023 Duy, Jeremy and Spencer -> [MIT License](https://github.com/jge162/ScoreBoard-wTimer/blob/main/License/MIT%20license)

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