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sar_adc_3.slx (44421, 2020-03-17)
基于噪声整形技术的模数转换器的设计_孙铁铭.pdf (2898804, 2020-03-17)

# Design of Analog to Digital Converter Based on Noise Shaping Technology Design noise-shaping SAR ADC model using Simulink. ## Mixed Signal Circuit Design -- behavior level An internal circuit-level DAC is used to introduce non-ideal factors of SAR ADC. Simulation shows that under the sampling rate of 20MS/s and oversampling rate of 4, the ideal first-order and second-order noise shaping is 1.1 bits and 0.77 bits higher than the original ADC. For the non-ideal 2nd-order noise shaping diagram, ENOB is improved by 1.73 bits compared with the original ADC under the sampling rate of 30MS/s, oversampling rate of 8, adding sample-and-hold circuit & noise shaping circuit capacitance noise.

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