SystemVerilog
所属分类：硬件设计
开发工具：SystemVerilog
文件大小：570KB
下载次数：0
上传日期：2020-11-06 09:42:55
上 传 者：
sh-1993
说明： SystemVerilog编程-用于建模、设计、模拟和测试的硬件描述和硬件验证语言...
(Programming in SystemVerilog - hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems.)
文件列表:
Changelog (745, 2020-11-06)
Counter (0, 2020-11-06)
Counter\first_counter.sv (2989, 2020-11-06)
Counter\first_counter_tb.sv (2421, 2020-11-06)
FSM (0, 2020-11-06)
FSM\FSM.sv (2640, 2020-11-06)
FSM\FSM_tb.sv (1161, 2020-11-06)
IPbus (0, 2020-11-06)
IPbus\IPbus_init.txt (8, 2020-11-06)
IPbus\IPbus_testing_class.svh (3500, 2020-11-06)
IPbus\IPbus_testing_module.sv (1781, 2020-11-06)
IPbus\Issues.txt (873, 2020-11-06)
IPbus\register.txt (89, 2020-11-06)
IPbus\register_status.txt (108, 2020-11-06)
Protokó_ IPbus - format ramek.pptm (590611, 2020-11-06)
# SystemVerilog
Programming in SystemVerilog - hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems.
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