ieee1800_2017

所属分类:通讯编程
开发工具:Java
文件大小:391KB
下载次数:0
上传日期:2021-02-09 21:49:08
上 传 者sh-1993
说明:  SystemVerilog预处理器、lexer和解析器,带示例
(SystemVerilog preprocessor, lexer and parser with examples)

文件列表:
ANTLR_LICENSE (2699, 2021-02-10)
LICENSE (11357, 2021-02-10)
Makefile (782, 2021-02-10)
bin (0, 2021-02-10)
demo.sh (149, 2021-02-10)
src (0, 2021-02-10)
src\Makefile (1621, 2021-02-10)
src\Makefile.antlr (4930, 2021-02-10)
src\Makefile.ieee1800_2017 (794, 2021-02-10)
src\com (0, 2021-02-10)
src\com\veriktig (0, 2021-02-10)
src\com\veriktig\scandium (0, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017 (0, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\IEEE1800_2017LexerError.java (1239, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\IEEE1800_2017ParserError.java (1240, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\IEEE1800_2017PreprocessorListener.java (19194, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\IEEE1800_2017TextMacroDefinition.java (2429, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\IEEE1800_2017TextMacros.java (10854, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\grammar (0, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\grammar\IEEE1800_2017Lexer.g4 (21560, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\grammar\IEEE1800_2017Parser.g4 (177485, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\grammar\IEEE1800_2017PreprocessorLexer.g4 (7657, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\grammar\IEEE1800_2017PreprocessorParser.g4 (3059, 2021-02-10)
src\com\veriktig\scandium\ieee1800_2017\grammar\Makefile (1342, 2021-02-10)
src\examples (0, 2021-02-10)
src\examples\Example.java (6089, 2021-02-10)
src\examples\Makefile (1384, 2021-02-10)
src\examples\Makefile.examples (688, 2021-02-10)
src\examples\extractors (0, 2021-02-10)
src\examples\extractors\IEEE1800_2017ModuleExtractor.java (1889, 2021-02-10)
src\examples\extractors\IEEE1800_2017ParameterExtractor.java (16579, 2021-02-10)
src\examples\extractors\IEEE1800_2017PortExtractor.java (11271, 2021-02-10)
src\examples\linter (0, 2021-02-10)
src\examples\linter\Linter.java (10597, 2021-02-10)
src\examples\object_model (0, 2021-02-10)
src\examples\object_model\SVModule.java (2027, 2021-02-10)
src\examples\object_model\SVParameter.java (925, 2021-02-10)
... ...

# ieee1800_2017 SystemVerilog preprocessor, lexer and parser with examples ## Overview The preprocessor was inspired by the excellent **mcpp** by Kiyoshi Matsui. The lexer and parser are based on the [IEEE spec](https://ieeexplore.ieee.org/document/8299595). Any questions I had with the spec are marked **// FRED** in IEEE1800_2017Parser.g4. This project is designed so that it can used with [Project Scandium](https://github.com/veriktig/scandium). ## License The files in src/org are from The ANTRL Project and are covered by ANTLR_LICENSE. Other files and ANTLR modifications are covered by LICENSE. ## Building Type ```make``` ## Running Use ```./demo.sh ``` The Example program: 1. Runs the preprocessor and checks if any `define's are left defined. 2. Runs the lexer and parser. Optionally pretty-prints the parse tree. 3. Runs an example linter. 4. Extracts and prints module headers. ### Tools Required The project was built on: ``` Ubuntu 18.04.2 macOS 10.14.5 ``` using: ``` openjdk 11.0.3 2019-04-16 OpenJDK Runtime Environment (build 11.0.3+7-Ubuntu-1ubuntu218.04.1) OpenJDK ***-Bit Server VM (build 11.0.3+7-Ubuntu-1ubuntu218.04.1, mixed mode, sharing) ``` ## Other Projects * [ANTLR](http://www.antlr.org) ANother Tool for Language Recognition. BSD-3-clause license * [MCPP](http://mcpp.sourceforge.net) A portable C preprocessor. BSD-2-clause license ### Change Log * 1.0.1 Use curl instead of wget (for macOS) * 1.0.0 Initial Release

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