文件列表:

.travis.yml (1986, 2018-03-16)
LICENSE (1081, 2018-03-16)
TODO (923, 2018-03-16)
accelerators (0, 2018-03-16)
accelerators\DebugAccel (0, 2018-03-16)
accelerators\DebugAccel\DebugAccel.bsv (2059, 2018-03-16)
accelerators\DebugAccel\Makefrag (350, 2018-03-16)
accelerators\Makefile.accelerators (2508, 2018-03-16)
accelerators\StrLen (0, 2018-03-16)
accelerators\StrLen\Makefrag (378, 2018-03-16)
accelerators\StrLen\StrLen.bsv (4449, 2018-03-16)
backends (0, 2018-03-16)
backends\connectal (0, 2018-03-16)
backends\connectal\Makefile (6003, 2018-03-16)
backends\connectal\bsv (0, 2018-03-16)
backends\connectal\bsv\ProcConnectal.bsv (14963, 2018-03-16)
backends\connectal\bsv\SharedMemoryBridge.bsv (9285, 2018-03-16)
backends\connectal\cpp (0, 2018-03-16)
backends\connectal\cpp\CircularBuffer.hpp (3846, 2018-03-16)
backends\connectal\cpp\DeviceTree.cpp (2606, 2018-03-16)
backends\connectal\cpp\DeviceTree.hpp (1375, 2018-03-16)
backends\connectal\cpp\Devices.hpp (1513, 2018-03-16)
backends\connectal\cpp\ElfLoader.cpp (4751, 2018-03-16)
backends\connectal\cpp\ExternalMMIO.cpp (2687, 2018-03-16)
backends\connectal\cpp\ExternalMMIO.hpp (1827, 2018-03-16)
backends\connectal\cpp\HostInterface.cpp (2943, 2018-03-16)
backends\connectal\cpp\HostInterface.hpp (1982, 2018-03-16)
backends\connectal\cpp\NullTandemVerifier.hpp (2243, 2018-03-16)
backends\connectal\cpp\Platform.cpp (5738, 2018-03-16)
backends\connectal\cpp\Platform.hpp (2913, 2018-03-16)
backends\connectal\cpp\PrintTrace.cpp (6449, 2018-03-16)
backends\connectal\cpp\PrintTrace.hpp (1905, 2018-03-16)
backends\connectal\cpp\ProcControl.cpp (2384, 2018-03-16)
backends\connectal\cpp\ProcControl.hpp (2270, 2018-03-16)
backends\connectal\cpp\SpikeTandemVerifier.cpp (12849, 2018-03-16)
backends\connectal\cpp\SpikeTandemVerifier.hpp (2482, 2018-03-16)
... ...

Riscy Processors - Open-Sourced RISC-V Processors ================================================= This repository contains a collection of open-sourced RISC-V processors written in Bluespec System Verilog (BSV). These processors can be built with a variety of backends to use the processors in different simulation frameworks or FPGA. Currently the supported backends are Connectal and Verilator. Connectal is a generic framework that supports a variety of FPGAs and simulation targets. ## Getting Started How to get started with this repository (tested in Ubuntu 14.04): 1. Get all the submodules. $ git submodule update --init --recursive 2. Get dependencies for building the RISC-V toolchain and building using connectal. $ sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc python-ply 3. Build riscv-gnu-toolchain and riscv-tests. `build.sh` can be used to build custom toolchains by passing the desired RISC-V ISA string in all caps (eg: `./build.sh RV32IMC"). By default, `build.sh` builds the toolchain `tools/RV***G`. $ cd tools $ ./build.sh $ cd .. 4. Setup environment variables for the Riscy project. You should either use this script from the top-level directory of the Riscy repository, or you should change the variable `RISCY_HOME` in the script to be the path to the Riscy repository. $ source ./setup.sh 5. Get a newer version of Verilator. The version of Verilator in the Ubuntu package has a bug that prevents running our BSV designs. We use a PPA to provide a newer version of Verilator. $ sudo apt-add-repository -y ppa:jamey-hicks/connectal $ sudo apt-get update $ sudo apt-get install verilator 7. Build the multicycle processor using the connectal backend with its verilator target. $ cd procs/RV***G_multicycle $ make build.verilator 8. Simulate tests by running `./runtests.sh` and then select the `connectal (verilator)` backend and which tests to run

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