文件列表:

LICENSE (11357, 2022-06-25)
Makefile (6710, 2022-06-25)
def (0, 2022-06-25)
def\CaravelHost.def (5359748, 2022-06-25)
def\ExperiarCore.def (19564736, 2022-06-25)
def\Flash.def (1443826, 2022-06-25)
def\Peripherals.def (28430037, 2022-06-25)
def\Video.def (4051497, 2022-06-25)
def\WishboneInterconnect.def (7187801, 2022-06-25)
def\user_project_wrapper.def (2327474, 2022-06-25)
docs (0, 2022-06-25)
docs\Design (0, 2022-06-25)
docs\Design\.$ExperiarSoC.drawio.bkp (10435, 2022-06-25)
docs\Design\.$ExperiarSoC.drawio.dtmp (10460, 2022-06-25)
docs\Design\.$Macros.drawio.bkp (2939, 2022-06-25)
docs\Design\.$Macros.drawio.dtmp (2911, 2022-06-25)
docs\Design\.$MemoryMap.drawio.bkp (1535, 2022-06-25)
docs\Design\ExperiarSoC-Peripheral Device.png (84275, 2022-06-25)
docs\Design\ExperiarSoC-Peripheral.png (71118, 2022-06-25)
docs\Design\ExperiarSoC-WB Peripheral Slave.png (67924, 2022-06-25)
docs\Design\ExperiarSoC.drawio (10308, 2022-06-25)
docs\Design\ExperiarSoC.png (74913, 2022-06-25)
docs\Design\Macros.drawio (2935, 2022-06-25)
docs\Design\MacrosPlacement.png (27209, 2022-06-25)
docs\Design\MemoryMap.drawio (1731, 2022-06-25)
docs\Design\MemoryMap.png (23810, 2022-06-25)
docs\Design\MemoryMap.txt (5688, 2022-06-25)
docs\Images (0, 2022-06-25)
docs\Images\detailed.guide (632385, 2022-06-25)
docs\Images\detailed.guide.jpg (664843, 2022-06-25)
docs\Images\user_project_wrapper.png (4466531, 2022-06-25)
docs\Logs (0, 2022-06-25)
docs\Logs\CaravelHost (0, 2022-06-25)
docs\Logs\CaravelHost\errors.log (2330, 2022-06-25)
... ...

[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/Wevel/ExperiarSoC/actions/workflows/user_project_ci.yml) # ExperiarSoC RISC-V SoC designed for the Efabless Open MPW Program. This project  ## Features - Dual RV32I cores - Per core SRAM - JTAG interface - External flash controller - Shared video SRAM - Configurable VGA output - 3x UART ports + 1 internal to caravel - 1x SPI ports - 4x PWM counters with 4x separate outputs (2 are internal read only) ## Memory Map  ## Macro Layout

## Build Status - CaravelHost: Success - ExperiarCore: Success - Flash: Success - Peripherals: Success - Video: Success - WishboneInterconnect: Success - user_project_wrapper: Success # Tests ## RTL ### verify-coreArch-rtl: Success ### verify-corePC-rtl: Success ### verify-coreMemory-rtl: Success ### verify-flash-rtl: Success ### verify-memory-rtl: Success ### verify-peripheralsGPIO-rtl: Success ### verify-peripheralsPWM-rtl: Success ### verify-peripheralsSPI-rtl: Success ### verify-peripheralsUART-rtl: Success ### verify-video-rtl: Success (Not validating correct pixel data) ## GL ### verify-corePC-gl: Success ### verify-coreMemory-rtl: Success ### verify-flash-gl: Success ### verify-memory-gl: Success ### verify-peripheralsGPIO-gl: Success ### verify-peripheralsPWM-gl: Success ### verify-peripheralsSPI-gl: Success ### verify-peripheralsUART-gl: Success ### verify-video-gl: Success # Need to do - Update probe values - Check for any remaining errors - Add stall signal if two wishbone masters read from the same location at the same time - Fix some writes not correctly using byte mask - Fix interrupt cause signals not being gated by mie meaning that the wrong interrupt cause could be set # Could do - Misaligned architecture instructions - Look into simulation with CVC - Write macro level simulations to get more coverage due to shorter simulations - Add JTAG test - Add interrupt test - Add uart pin swapping - Page based flash controller - Tile map rendering - Fetch next instruction a clock cycle earlier so instructions only take 2 cycles - Allow JTAG to read from wishbone bus # Reference work and inspiration - [Zero to ASIC Course](https://www.zerotoasiccourse.com/): Complete course on ASIC design. Also has useful references and terminology definitions. - [Openlane Documentation](https://openlane-docs.readthedocs.io/en/rtd-develop/index.html): Reference for a lot of configuration. The [Variables](https://openlane-docs.readthedocs.io/en/rtd-develop/configuration/README.html) and [Hardening Macros](https://openlane-docs.readthedocs.io/en/rtd-develop/doc/hardening_macros.html#) pages have been particularity useful. - [Caravel Documentation](https://caravel-harness.readthedocs.io/en/latest/index.html): Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the [github repository](https://github.com/efabless/caravel/tree/main/docs/pdf). - [Riscduino](https://github.com/dineshannayya/riscduino): Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.

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