CN2
所属分类：处理器开发
开发工具：Verilog
文件大小：38648KB
下载次数：0
上传日期：2021-02-27 10:58:12
上 传 者：
sh-1993
说明： 实现EA-UNI进程或RISC-V
(Implementarea unui procesor RISC-V)
文件列表:
Cerinte Lucrari (0, 2021-02-27)
Cerinte Lucrari\Lucrarea 2.pdf (728681, 2021-02-27)
Cerinte Lucrari\Lucrarea 3.pdf (1017580, 2021-02-27)
Cerinte Lucrari\Tema_Lab_1_CN2.pdf (18159, 2021-02-27)
Computer Architecture A Quantitative Approach (5th edition).pdf (13106737, 2021-02-27)
CursuriCN2Decebal.pdf (21562233, 2021-02-27)
IMG (0, 2021-02-27)
IMG\Screenshot 2020-10-15 163048.jpg (68758, 2021-02-27)
IMG\Screenshot 2020-10-15 170233.jpg (13608, 2021-02-27)
IMG\Screenshot 2020-10-15 170458.jpg (25954, 2021-02-27)
Lab (0, 2021-02-27)
Lab\Lab1+2+3 (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2 (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache\wt (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache\wt\gui_handlers.wdf (7231, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache\wt\java_command_handlers.wdf (1607, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache\wt\project.wpc (58, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache\wt\webtalk_pa.xml (6524, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.cache\wt\xsim.wdf (252, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.hw (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.hw\Tema1_Lab_CN2.lpr (284, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.ip_user_files (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1 (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\compile.bat (831, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\compile.log (0, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\elaborate.bat (1171, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\elaborate.log (611, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\glbl.v (1762, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\hs_err_pid17244.log (86777, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\mux2_1_vlog.prj (280, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\simulare1.tcl (449, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\simulare1_behav.wdb (10048, 2021-02-27)
Lab\Lab1+2+3\Tema1_Lab_CN2\Tema1_Lab_CN2.sim\sim_1\behav\xsim\simulare1_vlog.prj (280, 2021-02-27)
... ...
# CN2
Contine Laboratoare Calculatoare Numerice 2 ACS
# Laboratoare
1. [Laboratorul 1](https://github.com/CristiSandu/CN2/tree/master/Lab/Lab1%2B2%2B3/Tema1_Lab_CN2) - MUX8:1,Registru Multifuncional si Pipeline
2. [Laboratorul 2](https://github.com/CristiSandu/CN2/tree/master/Lab/Lucrare2) - Prima parte dintr-un RISC V
3. [Laboratorul 3](https://github.com/CristiSandu/CN2/tree/master/Lab/Lucrare3) - Implementare finala RISC V
# Cerinte
- [Laborator 1](https://github.com/CristiSandu/CN2/blob/master/Cerinte%20Lucrari/Tema_Lab_1_CN2.pdf)
- [Laborator 2](https://github.com/CristiSandu/CN2/blob/master/Cerinte%20Lucrari/Lucrarea%202.pdf)
- [Laborator 3](https://github.com/CristiSandu/CN2/blob/master/Cerinte%20Lucrari/Lucrarea%203.pdf)
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