risc-v
所属分类：处理器开发
开发工具：SystemVerilog
文件大小：20KB
下载次数：0
上传日期：2020-08-12 00:38:45
上 传 者：
sh-1993
说明： RISC-V管道处理器，带危险检测单元和转发单元。仅在c...中发生2个时钟的管道暂停...
(RISC-V pipeline processor with Hazard Detection Unit and Forwarding Unit. Pipeline stall for 2 clocks occur only in case of RAW dependency.)
文件列表:
LICENSE (1069, 2020-08-12)
c (0, 2020-08-12)
c\counter (0, 2020-08-12)
c\counter\Makefile (1108, 2020-08-12)
c\counter\build (0, 2020-08-12)
c\counter\build\counter.map (4951, 2020-08-12)
c\counter\src (0, 2020-08-12)
c\counter\src\main.c (1973, 2020-08-12)
c\inc (0, 2020-08-12)
c\inc\link.ld (797, 2020-08-12)
c\inc\start.S (1117, 2020-08-12)
rtl (0, 2020-08-12)
rtl\imem_dmem_32.sv (3822, 2020-08-12)
rtl\riscv.sv (21712, 2020-08-12)
rtl\riscv_top.sv (5770, 2020-08-12)
scripts (0, 2020-08-12)
scripts\word_to_byte_mem.py (1598, 2020-08-12)
sim (0, 2020-08-12)
sim\CMakeLists.txt (947, 2020-08-12)
sim\LICENSE (1068, 2020-08-12)
sim\Makefile (3913, 2020-08-12)
sim\Makefile_obj (2504, 2020-08-12)
sim\config.json (145, 2020-08-12)
sim\cppsrc (0, 2020-08-12)
sim\cppsrc\main.cpp (191, 2020-08-12)
sim\index.js (41, 2020-08-12)
sim\input.vc (135, 2020-08-12)
sim\package.json (849, 2020-08-12)
sim\showsigs.gtkw (2823, 2020-08-12)
sim\test (0, 2020-08-12)
sim\test\basic.js (1273, 2020-08-12)
# riscv-sv
RISC-V rv32i implementation
# Dependencies
- RISC-V gcc tools
- Xilinx Vivado 2018.3 or later
Set the RISCV variable in the environment to the location of riscv gcc tools
# Run instructions
```bash
cd c/counter
make
Testbench is in tb. Set top module as riscv_top.sv
It has been tested on Arty S7 development board running at 150MHz.
```
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