six-alpha
所属分类：处理器开发
开发工具：VHDL
文件大小：217KB
下载次数：0
上传日期：2021-12-13 20:49:37
上 传 者：
sh-1993
说明： 基于累加器的4位处理器
(Accumulator-based 4-bit processor)
文件列表:
contributing.md (549, 2021-12-14)
doc (0, 2021-12-14)
doc\img (0, 2021-12-14)
doc\img\pipeline.png (32319, 2021-12-14)
doc\pdf (0, 2021-12-14)
doc\pdf\Six Alpha Programmer's manual.pdf (100833, 2021-12-14)
doc\pdf\Six Alpha schematic.pdf (11291, 2021-12-14)
doc\src (0, 2021-12-14)
doc\src\Six Alpha Programmer's manual.odt (83731, 2021-12-14)
doc\src\Six Alpha schematic.odg (17570, 2021-12-14)
impl (0, 2021-12-14)
impl\basys2 (0, 2021-12-14)
impl\basys2\src (0, 2021-12-14)
impl\basys2\src\core_dm_db2.ucf (788, 2021-12-14)
impl\basys2\src\core_dm_db2.vhd (2239, 2021-12-14)
impl\basys2\src\seven_seg_contr_db2.vhd (3019, 2021-12-14)
license (1076, 2021-12-14)
sim (0, 2021-12-14)
sim\alu_tb.vhd (1673, 2021-12-14)
sim\core_tb.vhd (1182, 2021-12-14)
sim\data_mem_tb.vhd (2545, 2021-12-14)
src (0, 2021-12-14)
src\alu.vhd (1657, 2021-12-14)
src\alu_const.vhd (550, 2021-12-14)
src\core.vhd (5456, 2021-12-14)
src\core_const.vhd (607, 2021-12-14)
src\data_mem.vhd (2228, 2021-12-14)
src\data_mem_const.vhd (354, 2021-12-14)
src\inst_mem.vhd (581, 2021-12-14)
src\programming.vhd (1059, 2021-12-14)
src\sim_data_types.vhd (1251, 2021-12-14)
... ...
# Six Alpha
Six Alpha is a 4-bit accumulator-based processor architecture implemented as a softcore processor described in VHDL. It is based on my [very first processor](https://github.com/dominiksalvet/six-alpha/blob/master/https://github.com/dominiksalvet/pcycle) I have created in VHDL from 2015, which was tested on an Altera FPGA board. Later, it was ported to Digilent Basys 2 board.
The next traits include:
* Harvard memory architecture
* May address up to 128 B of instructions
* May address up to 16 nibbles of data
* I/O ports in data memory address space
## Machine Code
If you are curious what the machine code of Six Alpha looks like, browse the [collection of such programs](https://github.com/dominiksalvet/six-alpha/blob/master/sw).
## Original Plan
The original intention was to design and release also the following Six processor.
### Six Beta
* Pipelining capability
* Instruction memory programming interface
## Useful Resources
* [support.md](https://github.com/dominiksalvet/six-alpha/blob/master/support.md) – questions, answers, help
* [contributing.md](https://github.com/dominiksalvet/six-alpha/blob/master/contributing.md) – how to get involve
* [license](https://github.com/dominiksalvet/six-alpha/blob/master/license) – author and license
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