文件列表:

Anexo 1 - Diagrama de Blocos.jpeg (640692, 2018-09-10)
Anexo 2 - RandomNumber (Máquina de Estados).jpg (51395, 2018-09-10)
Anexo 3 - CheckEnd (Máquina de Estados).jpg (78897, 2018-09-10)
Anexo 4 - Compare (Máquina de Estados).jpg (47920, 2018-09-10)
Apresenta__o (0, 2018-09-10)
Apresenta__o\FPGA-altera.jpg (121383, 2018-09-10)
Apresenta__o\Mastermind.pptx (1921652, 2018-09-10)
Bin7SegDecoder.vhd (1228, 2018-09-10)
Bin7SegDecoder.vhd.bak (1118, 2018-09-10)
Blink.vhd (983, 2018-09-10)
Blink.vhd.bak (679, 2018-09-10)
BlinkTb.vhd (825, 2018-09-10)
BlinkTb.vhd.bak (660, 2018-09-10)
ClkDividerN.vhd (704, 2018-09-10)
Compare.vhd.bak (1124, 2018-09-10)
Compare2.vhd (4373, 2018-09-10)
Compare2.vhd.bak (0, 2018-09-10)
Compare_Tb.vhd (1943, 2018-09-10)
Compare_Tb.vhd.bak (1061, 2018-09-10)
Counter4.vhd (785, 2018-09-10)
Counter4.vhd.bak (781, 2018-09-10)
Counter4Tb.vhd (836, 2018-09-10)
Counter4Tb.vhd.bak (723, 2018-09-10)
Counter9.vhd (1077, 2018-09-10)
Counter9.vhd.bak (1020, 2018-09-10)
Counter99.vhd (1342, 2018-09-10)
Counter99.vhd.bak (1284, 2018-09-10)
Counter9999.vhd (1886, 2018-09-10)
Counter9999.vhd.bak (1798, 2018-09-10)
Counter9999Tb.vhd (884, 2018-09-10)
Counter9999Tb.vhd.bak (754, 2018-09-10)
Debouncer.vhd (639, 2018-09-10)
Debouncer.vhd.bak (576, 2018-09-10)
Demultiplexer.vhd (594, 2018-09-10)
Demultiplexer.vhd.bak (492, 2018-09-10)
FreqDivider.vhd (691, 2018-09-10)
FreqDivider.vhd.bak (600, 2018-09-10)
LSD_REL.pdf (184646, 2018-09-10)
LSD_REL.tex (9074, 2018-09-10)
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# FPGA Mastermind Project presented on Digital Systems Labs course (Univerisdade de Aveiro), 2015. The application is done using Altera Quartus framework, and programs the FPGA with the mastermind game. Diogo Ferreira Eduardo Silva

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