WARP_Core
所属分类：处理器开发
开发工具：VHDL
文件大小：0KB
下载次数：0
上传日期：2020-05-25 08:21:54
上 传 者：
sh-1993
说明： Wilson AXI RISCV处理器内核，
(Wilson AXI RISCV Processor Core,)
文件列表:
001.history (27675, 2020-05-25)
AXI_Design/ (0, 2020-05-25)
AXI_Design/To_Do/ (0, 2020-05-25)
AXI_Design/To_Do/Riscv_31I.info (274, 2020-05-25)
AXI_Design/src/ (0, 2020-05-25)
AXI_Design/src/verilog/ (0, 2020-05-25)
AXI_Design/src/verilog/pc_regs.sv (653, 2020-05-25)
AXI_Design/src/vhdl/ (0, 2020-05-25)
AXI_Design/src/vhdl/pc_regs.vhd (1830, 2020-05-25)
AXI_Design/testbench/ (0, 2020-05-25)
AXI_Design/testbench/Makefile (508, 2020-05-25)
AXI_Design/testbench/test_pc_regs.py (3253, 2020-05-25)
Cores/ (0, 2020-05-25)
Debug/ (0, 2020-05-25)
Debug/debug.tcl (3099, 2020-05-25)
Docs/ (0, 2020-05-25)
Docs/2Gb_1_35V_DDR3L.pdf (3211468, 2020-05-25)
Docs/Basic_Plan.odt (17424, 2020-05-25)
Docs/Basic_Plan.pdf (21193, 2020-05-25)
Docs/LC3/ (0, 2020-05-25)
Docs/LC3/LC3_Diagram.jpg (200902, 2020-05-25)
Docs/LC3/LC3_Instructions.gif (25550, 2020-05-25)
Docs/LC3/PattPatelAppA.pdf (1755385, 2020-05-25)
Docs/LC3/PattPatelAppB.pdf (545361, 2020-05-25)
Docs/LC3/PattPatelAppC.pdf (860500, 2020-05-25)
Docs/LC3/PattPatelAppD.pdf (1332941, 2020-05-25)
Docs/LC3/PattPatelAppE.pdf (1088241, 2020-05-25)
Docs/MachineCode.xlsx (74046, 2020-05-25)
Docs/riscv-spec-v2.2.pdf (663267, 2020-05-25)
Docs/xc7a35ti_csg324_grp1.bsd (60598, 2020-05-25)
Projects/ (0, 2020-05-25)
... ...
# WARP_Core
Wilson AXI RISCV Processor Core
- [Website Documentation]( http://wilsoninspace.com/warp-core/) shows all the steps I went through in designing and testing this project.
## News
The Goal is design a working RISCV processor for the Artix-7 on the Arty Board
STEPS:
* EDAplayground for a System Verilog test bench and DUT
* Have test bench use UVM
* Move test bnech and DUT to open source software COCOTB, IVerilog, and GHDL
* Compare options
## Schedule
Check website for updates
## Info
This Project is now focused on designing a RISCV processor to use the AXI bus.
Try to keep projects to minimal
- bd.tcl, verilog/vhdl
## Settings
## Log
Moving away from designing my own processor from scratch
- [Docs](https://github.com/AEW2015/WARP_Core/tree/master/Docs) is for parts documentation and reference material
- [Projects](https://github.com/AEW2015/WARP_Core/tree/master/Projects) will contain the top level HDL for test and fun applications.
- [Cores](https://github.com/AEW2015/WARP_Core/tree/master/Cores) will hold all the completed cores.
This project is continuing from the Mimas V2 processor
- [Old Attempt](https://github.com/AEW2015/Mimas_V2)
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