文件列表:

Makefile (2461, 2021-12-29)
core.sv (53318, 2021-12-29)
core_l1d_l1i.sv (13853, 2021-12-29)
count_leading_zeros.sv (1032, 2021-12-29)
decode_mips32.sv (40956, 2021-12-29)
disassemble.cc (2215, 2021-12-29)
disassemble.hh (1493, 2021-12-29)
divider.sv (4129, 2021-12-29)
exec.sv (65898, 2021-12-29)
ext_mask.sv (1416, 2021-12-29)
find_first_set.sv (1097, 2021-12-29)
fp_add.sv (6878, 2021-12-29)
fp_compare.sv (2098, 2021-12-29)
fp_compare.vh (132, 2021-12-29)
fp_convert.sv (898, 2021-12-29)
fp_div.sv (5223, 2021-12-29)
fp_mul.sv (5522, 2021-12-29)
fp_special_cases.sv (1282, 2021-12-29)
fp_trunc.sv (1061, 2021-12-29)
fpu.sv (6593, 2021-12-29)
globals.hh (285, 2021-12-29)
helper.cc (3285, 2021-12-29)
helper.hh (3442, 2021-12-29)
interpret.cc (45182, 2021-12-29)
interpret.hh (9169, 2021-12-29)
interpret64.cc (41409, 2021-12-29)
l1d.sv (31441, 2021-12-29)
l1i.sv (27292, 2021-12-29)
linux_monitor.hh (572, 2021-12-29)
linux_o32_syscall.cc (6818, 2021-12-29)
linux_o32_syscall.hh (137, 2021-12-29)
loadelf.cc (10403, 2021-12-29)
loadelf.hh (142, 2021-12-29)
machine.vh (3380, 2021-12-29)
mul.sv (3860, 2021-12-29)
osx_elf.h (117729, 2021-12-29)
ram1r1w.sv (553, 2021-12-29)
ram2r1w.sv (848, 2021-12-29)
... ...

# mipscore Pedagogical SystemVerilog model for a decoupled MIPS CPU. Aspires to be used in either a FPGA implementation of a SGI workstation or N64. Implements most of user-level MIPS-2, some of MIPS-3, some of MIPS-4, and some of MIPS32/MIPS64 Only 32b code has been tested. Correctness checking infrastructure only really supports 32b MIPS too. Floating-point implementation is correctness challenged. Correct implementation of floating-point algorithms tricker than previously believed ;) Relatively simple uarch - scalar renamed, decoupled microarchitecture. 1 mem FU, 1 int FU, and FPU. Each FU is backed by an in order FIFO scheduler. E.g., within each FU, instructions are scheduled in order but only true dependences prevent execution across execution classes. Caches - direct mapped. Keep things simple and actually implementable on FPGA. Fetch - one instruction per cycle from the I$. Branch targets decoded directly from the I$ and correctly predicted direct branches have no penality. 64 entry BTB for indirect branches. 4 entry RSB for indirects. Sizes configurable in the "machine.vh" configuration header. Instructions pushed into queue for decode. Decode - straightforward implementation. uops placed in allocation queue. Allocate - Check for sufficient resources (ROB entry, physical registers, space in the appropriate FU queue). Allocate a renamed register from the appropriate register pool, if required. Read RAT to map logical registers to physical registers. Update RAT if uop writes a dest. Some instructions are folded and immediately mark complete after allocation (e.g., direct jumps or nops), they do not take execution slots. Allocation RAT immediately updated. Executation - Complete - Graduate - (yes, using R10k terminology)

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