文件列表:

.vscode/ (0, 2023-11-12)
.vscode/settings.json (963, 2023-11-12)
PROGRAMMING.md (5726, 2023-11-12)
edif-parse/ (0, 2023-11-12)
edif-parse/edif2dot.py (5080, 2023-11-12)
edif-parse/edif2v.py (509, 2023-11-12)
edif-parse/edif_and_simplified_graphviz.png (104839, 2023-11-12)
edif-parse/edifsimplify.py (1718, 2023-11-12)
edif-parse/ediftimestamp.sh (669, 2023-11-12)
examples/ (0, 2023-11-12)
examples/buf_inv.PLD (1047, 2023-11-12)
examples/buffer.PLD (1128, 2023-11-12)
linux-workflow/ (0, 2023-11-12)
linux-workflow/5vcomp (12683, 2023-11-12)
linux-workflow/5vcomp.desktop (201, 2023-11-12)
linux-workflow/5vpld.xml (1609, 2023-11-12)
util/ (0, 2023-11-12)
util/5vpins (8570, 2023-11-12)
util/jesd3.py (13170, 2023-11-12)
vendor-datasheets/ (0, 2023-11-12)
vendor-datasheets/doc0735.pdf (1957410, 2023-11-12)
vendor-docs/ (0, 2023-11-12)
vendor-docs/CPLD_Mentor_Verilog_tutorial[1].pdf (1985296, 2023-11-12)
vendor-docs/CUPL_USERS_GUIDE.pdf (1088219, 2023-11-12)
vendor-docs/WinCUPL-data-flow-diagram.png (14351, 2023-11-12)
vendor-docs/fitter.pdf (247795, 2023-11-12)
windows-workflow/ (0, 2023-11-12)
windows-workflow/5vcomp.bat (4192, 2023-11-12)
windows-workflow/5vinstall.bat (2372, 2023-11-12)
windows-workflow/context-menu-pld-5vcomp.reg (252, 2023-11-12)

# Overview This repository centers around documenting modern ways of developing logic for and programming Atmel (Now Microchip) 5V GAL PLD and CPLD parts under recent Linux (Ubuntu 22.04) and Windows 10 22H2 versions. * ATF16V8 (Modern/active equivalent of the PAL16V8 and GAL16V8 parts) *  (Modern/active equivalent of the PAL22V10 and GAL22V10 parts) * ATF1502 * ATF1504 * ATF1508 These parts are still active and highly worth considering wherever: * 5V logic is a requirement, avoiding level shifting, low latency (7ns), instant-on & non-volatile. * Prototyping / Iteration (reprogrammable) * Learning about logic: Through-hole / soldering-friendly is desired: All 16V8 or 22V10 parts are available in DIP packages; ATF150x parts are available in PLCC packages that can be placed in through-hole PLCC sockets. SMD packages are available for any of the parts. * Replacing large quantities of various TTL/CMOS Logic Gates (74-series logic) This is a "Choose your own adventure novel". Covered here are many approaches and tradeoffs: * Using the WinCUPL IDE (Erratic, unreliable) * Using just the CUPL.EXE compiler from WinCUPL directly with some wrapper scripts here (5vcomp). Works in Windows/Linux. (recommended) * Using Quartus (only for the CPLD. Works by first targeting a similar Altera CPLD and then using the POF2JED utility to convert.) Windows/Linux * Making your own fusemap / .JED file with nothing more than a datasheet and text editor. Maybe need some graph paper... * Experimental approaches with Yosys (Only for the CPLD parts. EDIF is fed into the Atmel fitter) * Several Approaches to reverse-engineering a .JED file back into logic equations. This is mostly a collection of documentation, but if you are interested in using CUPL.EXE directly, some small scripts (5vcomp) are here that help make things easier and provide examples on how to avoid WinCUPL while still utilizing these parts: *  * 

Scope: Expand here for why similar parts not covered

* We only consider true 5V parts (not merely parts with 5V tolerant inputs, of which there are many more). * 3.3V parts cannot supply the minimum of 3.6V to drive the input of a 5V CMOS part high, so 5V tolerant parts are not enugh in many cases. * Notably, however, driving 5V TTL inputs from a 3.3V part, on the other hand, is not a problem. A 5V TTL input has a threshold of 2V. * 3.3V parts are not considered: There are simply better choices that are well documented. Also, the CPLD parts have VccIO inputs, so you can technically use them in 3.3V designs just as well. * The Greekpak devices probably should be covered here, but, they're reasonably well documented with modern tools. * Any parts that are NRND or inactive are not covered, as we consider what can be reliably and sensibly purchased. * Since all of the parts considered here are still in full production (as of 2023), they can be used in production designs. * For the ATF150x CPLD parts specifically: * The BE and ASV devices not covered here as they seem to be difficult to obtain and are not 5V devices. If you need 3.3V or lower, there are probably better parts suited to your needs.

# Background on digital logic. This repository isn't intended to be an introduction to digital logic, but a brief review and compare/contrast to similar things is provided here.

Expand here for tutorials on Digital Logic

Ben Eater does a series of Videos on Digital Logic that are a really excellent introduction to some of the concepts here.

Expand here for a description of how these parts compare to ladder logic on a PLC

* Each rung's output in ladder-logic can be thought of as a single macrocell. * The inputs on a rung can be "normally open" or "normally closed" (active high or low), and can consist of any number of inputs (or even the state of another macrocell). The inputs defined on a single rung are basically equivalent to a single product-term belonging to a macrocell. There can be multiple product terms defined that activate a given macrocell.

Expand here for details on how all of these compare to FPGAs

Such parts are the spiritual predecessors of more modern FPGAs. Key differences between FPGAs and PLDs: * FPGAs are typically constructed from a large number of LUTs (Lookup tables). CPLDs use a sum-of-products structure. * FPGAs typically expect to have their bitstream uploaded on powerup, requiring an external EEPROM. PLDs are typically non-volatile and instantly ready upon powerup. * FPGAs usually support more standard means of programming, whereas many PLDs required specialized device programmers. * There are likely exceptions to all of the above in some parts. These are not hard rules.

# Requirements A high-level overview of what is required: * Basic understanding of digital logic. * The actual PLD/CPLD chip you'd like to work with from the usual suppliers (Mouser, Digikey, Octopart) * A software workflow covered here. Highly recommended is using the 5vcomp script from here to call the CUPL.EXE compiler. This works on Linux and even Windows 10 22H2 x64! * An EPROM/Device programmer if you wish to use the ATF16V8 or ATF22V10 parts. * An EPROM or JTAG programmer for the ATF150x parts  for details on what it takes to program these parts in detail. # Terminology & File Formats PLD/GAL - Programmable Logic Device. Small, generally DIP-package 5V programmable Logic.
CPLD - Complex Programmable Logic Device. Larger packages, many pins, much more complex.
5vcomp - A utility in this repository (batch file for Windows / shell script for linux) that is a wrapper around the CUPL.EXE compiler
Combinatorial Logic - Simple logic (AND, OR, NOT, gates, etc.) that does not use flip-flops / registers / clocks. Such logic could technically be implemented with an EPROM/Memory, where a series of inputs always maps to a known set of outputs.
Registered Logic - Logic that uses registers (flip-flops), and can thus hold state. On the GAL16V8 and GAL22V10, each macrocell can be configured as a D-Flip-Flop, and all flip-flops share the same clock pin. On the ATF150x, much more complex types of registered logic and clocking options are available. Macrocell - Each output has a macrocell associated with it. These can often be configured as active high, active low, flip-flops, etc.
Product Term - Each macrocell has a number of product terms associated with it (typically around 5). A product term is essentially a giant AND gate with inputs to each pin on the device. Burning away fuses allows selecting which inputs are fed into this AND gate, ultimately selecting the conditions required for a product term to be activated. Product terms belonging to the same output macrocell are then combined into an OR gate before being fed into the macrocell. This means that there can be several combination of inputs that allow a given macrocell to be triggered. This architecture is called a Sum-of-Products logic array. CUPL - A early (1983) programming language used to define the behavior of digital logic gates. "Compiler for Universal Programmable Logic.", is essentially a predecessor to languages like Verilog/VHDL. CUPL.EXE is the compiler which is used to compile .PLD files written in CUPL, ultimately to be burned into programmable logic devices.
WinCUPL - A Windows front-end/IDE to the CUPL compiler and related programs. It is still part specifically that we are trying to avoid, while keeping everything else underneath/around it as it is buggy.
.dl File - Device Library File. This file determines what devices CUPL has the ability to compile for.
.cat File - A text file corresponding to a .dl device library file with the same name and containing a list of supported devices by CUPL. Netlist - A netlist is essentially an electrical schematic in a text file which defines connections. For the purposes here, it is an intermediary file format (Either EDIF or Berkeley PLA), which is used to describe the behavior of logic ultimately fed into the fitter.
.TT2 - The Berkeley PLA file format. An intermediary file which CUPL.EXE can generate that can be used by the Atmel fitters.
.EDF / .EDN - EDIF is another type of netlist format. The Atmel fitter can use this as both an input, as well as an output. Yosys is capable of generating this format, however, one will still need a techmap for this to work.
Fitter - A fitter converts a netlist into the fusemap (.JED) file. Fitters are needed for the ATF150x CPLD devices. In more modern parlance, this is basically place & route.
ATMEL.STD File - Part of the Atmel ATF150x fitter, the primitive/device library for PLA.[^1]
APRIM.LIB File - Part of the Atmel ATF150x fitter, the primitive/device library for EDIF.[^1] .JED/JEDEC File - A fuse map intended to be "burned/programmed" into a logic device. .SVF File - Serial Vector Format. Generated from the .JED file, the .SVF can be used by any JTAG programmer (vendor-independent) to program a device that has a JTAG interface.
CSIM - A tool for simulating the behavior of logic. This takes an .SI file and produces an .SO file. This is not concerned with timing, but simply logic states. Wine - Wine is not an emulator. Allows running Windows programs under Linux.
# Writing logic for these parts: Possible Workflows Each of the subsections here represents a potential workflow to design logic equations for these parts. The majority of the focus will be on methods that avoid WinCUPL (which is ultimately just an IDE/text-editor that calls CUPL.EXE). Some of the other approaches covered here also avoid the CUPL compiler as well and instead generate netlists provided directly to the device fitter. Finally, a word on preferred approach, given the options: Using the CUPL.EXE compiler via command line or Quartus are probably the best ways, especially if you are interested in using Hi-Z states. Neither Yosys nor Digital seemed to have robust support for Hi-Z states (important for Bidirectional I/O). This diagram is from the help files built into WinCUPL which shows how one can go from a CUPL .PLD into the .JED files needed to program a device.  ## Old Approach: WinCUPL (16V8, 22V10, and ATF150x) WinCUPL is basically an IDE, possibly before the term IDE came into existance. While logic for these parts can be written using WinCUPL itself, the experience may be fraught with difficulty as it is a quirky and often unstable Windows application (While it does run great under Wine, this doesn't really change things much). I've seen the editor itself crash just for looking at it sideways, and its copy-paste functionality behave in bewildering ways. It does however have value in the help files / documentation / examples. It should emphasized that the CUPL compiler itself is actually pretty solid/stable, and so the troubles of WinCUPL shouldn't be equated with CUPL itself. So, the recommended approach is to install and use it for documentation/examples/compiler/device-library and then simply avoid it for serious work by using the command line CUPL.EXE (perhaps through the 5vcomp helper scripts in this repository as in the next section). You can Download WinCUPL from here. To get it working under Linux with Wine, you'll need winetricks so you can install mfc40 and mfc42. On Ubuntu Linux, this would look something like: sudo apt-get install wine winetricks playonlinux winetricks mfc40 mfc42 Furthermore, if you are intending on working with the ATF150x parts, you should probably grab the newer fitters out of the Atmel Prochip package. The utilities in this repository will refuse to work with the old fitters. ## 5vcomp: The CUPL compiler & Your favorite text editor or IDE (16V8, 22V10, and ATF150x) Since WinCUPL simply is a front-end / IDE on top of the CUPL.EXE compiler and related programs, one can write the desired logic in CUPL, save it in a .PLD file using their favorite editor and have CUPL.EXE compile it into a .JED file for programming into a PLD. 5vcomp is a simple wrapper around the CUPL compiler. This is probably the most solid approach assuming you are OK with using CUPL as a language. You should start with the WinCUPL approach as a prerequisite since it installs the CUPL compiler and has examples/help files. The workflows here simply make this easier/conveinent by catching a lot of common issues and providing reasonable defaults to the compiler: *  *  ## Guide to CUPL itself Assuming you're using CUPL either through WinCUPL or 5vcomp, this section has a general reference to the language, device library details, etc. 

Expand here for details of the command line flags for CUPL.EXE

Run CUPL using the following command line format: cupl [-flags] [library] [device] source where -flags is the following set of compiler options: -j JEDEC download format -h ASCII-HEX download format -i HL download format -n use input filename for output file -a create absolute file -l create listing file -e create expanded macro definition file -x create expanded product-terms in documentation file -f create fuse plot/chip diagram in documentation file -p create PDIF database interchange format file -b create Berkeley PLA format file -c create PALASM format file -d deactivate unused OR terms -r disable product term merging -g program security fuse -o treat all state machines as “one-hot” -u use specified library for compilation -s perform logic simulation after compilation -w perform simulation with waveform output (MS-DOS only) -m0 no minimization -m1 quick minimization (default) -m2 Quine McCluskey -m3 Presto -m4 Expresso -q MIcrosoft format for error messages -zq QuickLogic’s QDIF file -kb Optimize product term usage for pin or pinnode variables. This overrides the DEMORGAN statement if it appears in the source file -kd DeMorganize all pin and pinnode variables. This overrides the DEMORGAN statement if it appears in the source file -ks Force product term sharing during minimization. This is also referred to as group reduction -kx Do not expand XOR to AND-OR equations. This is used for device independent designs or designs targeted for fitter-supported devices where the fitter supports XOR gates

Expand here if you are interested in using VS Code as an IDE

Recently, two different extensions for VS Code for CUPL have been written: * https://marketplace.visualstudio.com/items?itemName=tlgkccampbell.code-cupl * This one handles just syntax highlighting for CUPL .PLD files * https://marketplace.visualstudio.com/items?itemName=VaynerSystems.VS-Cupl * This is an entire workflow, which has a bit more functionality beyond just syntax highlighting.

Expand here for a list of devices Atmel WinCUPL supports

* CBLD.EXE will allow you to see a list of devices that are supported within the CUPL.DL device library. * Atmel WinCUPL is limited Atmel devices, however, other versions of CUPL found elsewhere will have parts from a broader array of manufacturers. wine ./cbld.exe -l CBLD(PM): CUPL Device Library Management Program Version 5.0a Copyright (c) 1983, 1998 Logical Devices, Inc. C:\Wincupl\Shared\CUPL.DL rev:DLIB-h Device Rev Pins Fuses Pterms ------------ --- ---- ----- ------ v750 03 24 14394 171 v750b 02 24 14435 171 v750c 02 24 14504 171 v750cext 02 24 14504 171 v750cextppk 02 24 14504 171 v750cppk 02 24 14504 171 v2500 07 40 71648 416 v2500b 04 40 71745 416 v2500c 04 40 71816 416 v2500cppk 04 40 71816 416 f1500 01 44 15360 320 f1500t 01 44 15360 320 f1500a 01 44 15360 320 f1500at 01 44 15360 320 f1502plcc44 01 44 15360 320 f1502ispplcc44 01 44 15360 320 f1502tqfp44 01 44 15360 320 f1502isptqfp44 01 44 15360 320 f1504plcc44 01 44 15360 320 f1504ispplcc44 01 44 15360 320 f1504tqfp44 01 44 15360 320 f1504isptqfp44 01 44 15360 320 f1504plcc68 02 68 15360 320 f1504ispplcc68 02 68 15360 320 f1504plcc84 02 84 15360 320 f1504ispplcc84 02 84 15360 320 f1504qfp100 02 100 15360 320 f1504ispqfp100 02 100 15360 320 f1504tqfp100 02 100 15360 320 f1504isptqfp100 02 100 15360 320 f1508plcc84 02 84 15360 320 f1508ispplcc84 02 84 15360 320 f1508qfp100 02 100 15360 320 f1508ispqfp100 02 100 15360 320 f1508tqfp100 02 100 15360 320 f1508isptqfp100 02 100 15360 320 f1508pqfp160 01 160 15360 320 f1508isppqfp160 01 160 15360 320 atfvirtual 01 44 99999 5000 g16v8 09 20 2194 64 g16v8ma 08 20 2194 64 g16v8ms 11 20 2194 64 g16v8a 03 20 2194 64 g16v8as 02 20 2194 64 g16v8s 09 20 2194 64 g16v8cpms 01 20 2195 64 g16v8cp 01 20 2195 64 g16v8cpas 01 20 2195 64 g16v8cpma 01 20 2195 64 g20v8 03 24 2706 64 g20v8ma 03 24 2706 64 g20v8ms 03 24 2706 64 g20v8a 02 24 2706 64 g20v8as 01 24 2706 64 g20v8cp 02 24 2707 64 g20v8cps 01 24 2707 64 g20v8cpm ... ...