文件列表:

modelsim/ (0, 2023-07-30)
modelsim/bf-processor.cr.mti (7160, 2023-07-30)
modelsim/bf-processor.mpf (21654, 2023-07-30)
modelsim/transcript (802, 2023-07-30)
quartus/ (0, 2023-07-30)
quartus/bf-processor.qpf (1326, 2023-07-30)
quartus/bf-processor.qsf (4329, 2023-07-30)
quartus/bf-processor_nativelink_simulation.rpt (1240, 2023-07-30)
screenshots/ (0, 2023-07-30)
screenshots/bf_datapath.png (57728, 2023-07-30)
screenshots/instr_datapath.png (84915, 2023-07-30)
screenshots/io_datapath.png (68045, 2023-07-30)
screenshots/jp_datapath.png (55087, 2023-07-30)
screenshots/mem_datapath.png (76697, 2023-07-30)
src/ (0, 2023-07-30)
src/addersubtractor.vhd (658, 2023-07-30)
src/bf_processor.vhd (3235, 2023-07-30)
src/instrdecoder.vhd (1391, 2023-07-30)
src/instruction_datapath.vhd (1948, 2023-07-30)
src/io_datapath.vhd (799, 2023-07-30)
src/is_zero.vhd (344, 2023-07-30)
src/jumping_datapath.vhd (1865, 2023-07-30)
src/memory_datapath.vhd (2463, 2023-07-30)
src/mux2.vhd (338, 2023-07-30)
src/regbank.vhd (1238, 2023-07-30)
src/registry.vhd (561, 2023-07-30)
testbenches/ (0, 2023-07-30)
testbenches/input_data_from_file.vhd (1642, 2023-07-30)
testbenches/instrs_from_file.vhd (1972, 2023-07-30)
testbenches/memory-dp-test.txt (276, 2023-07-30)
testbenches/testbench_bf_processor.vhd (2953, 2023-07-30)
testbenches/testbench_memory_datapath.vhd (3002, 2023-07-30)
testbenches/tests/ (0, 2023-07-30)
testbenches/tests/test01-input.txt (0, 2023-07-30)
testbenches/tests/test01.bf (750, 2023-07-30)
testbenches/tests/test02-input.txt (0, 2023-07-30)
testbenches/tests/test02.bf (253, 2023-07-30)

# Brainf\*ck Processor This is project with the goal of implementing a brainf\*ck interpreter in hardware, creating a processor that uses brainf\*ck as its architecture. This first version separates the memory of the program from the memory that hold the instructions, and implements a branching logic, that although simple, creates a slow runtime when the program uses too many loops. ## Micro Architecture The processor is separated in 4 main datapaths.  ### Memory Datapath Handles the `+-><` instructions.  #### Intruction Datapath Stores and decodes the instructions. It has pins (`PC` and `Instruction`) that are to be used to add external "EEPROMS" on testbenches. If the `Instruction` returned by the memory element isn't one of these ascii characters `+-><[].,` the processor will have a undefined behaviour.  ## Jumping Datapath Handles the `[]`instructions.  ### IO Datapath Handles the `.,` instructions.  ## Tools Used This project was developed with Quartus Prime Lite (2020) (from this [nix package](https://github.com/loco-choco/bf-processor/blob/master/https://github.com/NixOS/nixpkgs/blob/nixos-23.05/pkgs/applications/editors/quartus-prime/default.nix)) and uses VHDL as its main HDL language. The testbenches were coded for usage in the ModelSim that comes with Quartus. ## Statistics These are statistics from compiling the top entity `bf_datapath` on Quartus for a MAX 10 device. | Type | Number | |---|---| | Logic Elements | 2736 | | Registers | 2120 | | Pins | 52 | Execution times of different bf programs from ModelSim simulation. | .bf file | Name in Testbench | Execution Time (ns)| |---|---|---| | [Adding two values](https://github.com/loco-choco/bf-processor/blob/master/https://en.wikipedia.org/wiki/Brainfuck#Adding_two_values) | test01.bf | 1346 | | [Ola Mundo!](https://github.com/loco-choco/bf-processor/blob/master/https://pt.wikipedia.org/wiki/Brainfuck#Programa_Ol%C3%A1_Mundo) | test02.bf | 13850 |

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