spi_driver_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1815KB
下载次数：13
上传日期：2011-11-07 20:08:33
上 传 者：
1008508
说明： SPI控制器RTL级源码，实现标准SPI硬件接口
(SPI controller RTL-level source code to achieve the standard SPI hardware interface)
文件列表:
spi\tags\asyst_2\rtl\verilog\spi_clgen.v (5111, 2003-07-04)
spi\tags\asyst_2\rtl\verilog\spi_defines.v (6302, 2003-07-04)
spi\tags\asyst_2\rtl\verilog\spi_shift.v (9442, 2003-07-08)
spi\tags\asyst_2\rtl\verilog\spi_top.v (12506, 2003-07-08)
spi\tags\asyst_2\rtl\verilog\timescale.v (23, 2002-06-12)
spi\tags\asyst_3\rtl\verilog\spi_clgen.v (5111, 2003-07-04)
spi\tags\asyst_3\rtl\verilog\spi_defines.v (6302, 2003-07-04)
spi\tags\asyst_3\rtl\verilog\spi_shift.v (9442, 2003-07-08)
spi\tags\asyst_3\rtl\verilog\spi_top.v (12506, 2003-07-08)
spi\tags\asyst_3\rtl\verilog\timescale.v (23, 2002-06-12)
spi\tags\initial\bench\verilog\spi_slave_model.v (3628, 2002-06-12)
spi\tags\initial\bench\verilog\tb_spi_top.v (14427, 2002-06-12)
spi\tags\initial\bench\verilog\wb_master_model.v (5722, 2002-06-12)
spi\tags\initial\doc\src\spi.doc (5814272, 2002-06-12)
spi\tags\initial\rtl\verilog\spi_clgen.v (4940, 2002-06-12)
spi\tags\initial\rtl\verilog\spi_defines.v (3914, 2002-06-12)
spi\tags\initial\rtl\verilog\spi_shift.v (6419, 2002-06-12)
spi\tags\initial\rtl\verilog\spi_top.v (10097, 2002-06-12)
spi\tags\initial\rtl\verilog\timescale.v (23, 2002-06-12)
spi\tags\initial\sim\run\sim (369, 2002-06-12)
spi\tags\initial\sim\run\tcl.scr (154, 2002-06-12)
spi\tags\rel_1\bench\verilog\spi_slave_model.v (3628, 2002-06-12)
spi\tags\rel_1\bench\verilog\tb_spi_top.v (14427, 2002-06-12)
spi\tags\rel_1\bench\verilog\wb_master_model.v (5722, 2002-06-12)
spi\tags\rel_1\doc\spi.pdf (61705, 2002-07-13)
spi\tags\rel_1\doc\src\spi.doc (733184, 2002-07-13)
spi\tags\rel_1\rtl\verilog\spi_clgen.v (4940, 2002-06-12)
spi\tags\rel_1\rtl\verilog\spi_defines.v (3914, 2002-06-12)
spi\tags\rel_1\rtl\verilog\spi_shift.v (6419, 2002-06-12)
spi\tags\rel_1\rtl\verilog\spi_top.v (10097, 2002-06-12)
spi\tags\rel_1\rtl\verilog\timescale.v (23, 2002-06-12)
spi\tags\rel_1\sim\run\sim (369, 2002-06-12)
spi\tags\rel_1\sim\run\tcl.scr (154, 2002-06-12)
spi\tags\rel_2\bench\verilog\spi_slave_model.v (3637, 2003-03-27)
spi\tags\rel_2\bench\verilog\tb_spi_top.v (12193, 2003-04-16)
spi\tags\rel_2\bench\verilog\wb_master_model.v (5722, 2002-06-12)
spi\tags\rel_2\doc\spi.pdf (80127, 2003-04-16)
spi\tags\rel_2\doc\src\spi.doc (1513472, 2003-04-16)
spi\tags\rel_2\rtl\verilog\spi_clgen.v (5123, 2003-04-16)
spi\tags\rel_2\rtl\verilog\spi_defines.v (4358, 2003-04-16)
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