说明：  一个Perl-Tk应用程序，在加利福尼亚州运行大型数字电路设计的回归测试套件（用Verilog、VHDL或SystemVerilog.编写）...，
(A Perl Tk application that runs regression test suites of large digital circuit designs (written in Verilog, VHDL or SystemVerilog) on Cadence Incisive tools, keeps track of coverage data, driven by a (XML) verification plan.)