stopwatch_verilog
所属分类：硬件设计
开发工具：HTML
文件大小：0KB
下载次数：0
上传日期：2022-04-25 22:22:49
上 传 者：
sh-1993
说明： 本项目专注于使用Nexys A7 FPGA采用自顶向下的方法设计秒表电路，其中我们从了解......开始...，
(This project is focused on the design of a stopwatch circuit using a top-down approach using Nexys A7 FPGA, where we start by understanding the design process by which we clearly define the problem to be solved, outlined the functions of a desired circuit, and then combined digital building blocks to realize the desired function of the circuit.)
文件列表:
Lab 10/ (0, 2022-04-25)
Lab 10/clkdiv.sv (1931, 2022-04-25)
Lab 10/counter_bcd.sv (829, 2022-04-25)
Lab 10/debounce.sv (1305, 2022-04-25)
Lab 10/single_pulser.sv (1090, 2022-04-25)
RTL/ (0, 2022-04-25)
RTL/clkdiv.sv (1008, 2022-04-25)
RTL/count_3bit.sv (810, 2022-04-25)
RTL/counter_bcd.sv (772, 2022-04-25)
RTL/counter_bcd1.sv (773, 2022-04-25)
RTL/debounce.sv (1176, 2022-04-25)
RTL/dec_3_8.sv (927, 2022-04-25)
RTL/lab10_top.sv (2085, 2022-04-25)
RTL/multiple_bcd.sv (1050, 2022-04-25)
RTL/multiple_bcd1.sv (1051, 2022-04-25)
RTL/multiple_bcd_tb1.sv (1394, 2022-04-25)
RTL/mux_8_1.sv (911, 2022-04-25)
RTL/register.sv (660, 2022-04-25)
RTL/sevenseg_control.sv (1118, 2022-04-25)
RTL/sevenseg_hex.sv (1169, 2022-04-25)
RTL/single_pulser.sv (727, 2022-04-25)
RTL/stopwatch_fsm.sv (1381, 2022-04-25)
Simulation/ (0, 2022-04-25)
Simulation/multiple_bcd_tb.sv (1378, 2022-04-25)
Simulation/stopwatch_fsm.sv (519, 2022-04-25)
Simulation/stopwatch_fsm_tb.sv (1225, 2022-04-25)
System_Verliog_Stopwatch.pdf (770686, 2022-04-25)
project_1/ (0, 2022-04-25)
project_1/project_1.cache/ (0, 2022-04-25)
project_1/project_1.cache/wt/ (0, 2022-04-25)
project_1/project_1.cache/wt/gui_handlers.wdf (12462, 2022-04-25)
project_1/project_1.cache/wt/java_command_handlers.wdf (2794, 2022-04-25)
project_1/project_1.cache/wt/project.wpc (121, 2022-04-25)
project_1/project_1.cache/wt/synthesis.wdf (5843, 2022-04-25)
project_1/project_1.cache/wt/synthesis_details.wdf (100, 2022-04-25)
project_1/project_1.cache/wt/webtalk_pa.xml (10429, 2022-04-25)
project_1/project_1.cache/wt/xsim.wdf (256, 2022-04-25)
project_1/project_1.hw/ (0, 2022-04-25)
project_1/project_1.hw/hw_1/ (0, 2022-04-25)
project_1/project_1.hw/hw_1/hw.xml (789, 2022-04-25)
... ...
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