Verilog
所属分类：硬件设计
开发工具：Verilog
文件大小：0KB
下载次数：0
上传日期：2023-01-10 07:09:08
上 传 者：
sh-1993
说明： 使用Icarus Verilog和GTKWave作为波形查看器设计和测试的简单Verilog-Gates，
(Simple Verilog Gates designed and tested with Icarus Verilog and GTKWave as a waveform viewer,)
文件列表:
.DS_Store (6148, 2023-01-09)
Basics/ (0, 2023-01-09)
Basics/.DS_Store (6148, 2023-01-09)
Basics/7458-Chip/ (0, 2023-01-09)
Basics/7458-Chip/7458-chip.v (1185, 2023-01-09)
Basics/7458-Chip/7458-chip.vvp (5528, 2023-01-09)
Basics/7458-Chip/7458_chip.vcd (2415, 2023-01-09)
Basics/7458-Chip/output.txt (2676, 2023-01-09)
Basics/declaring-wires/ (0, 2023-01-09)
Basics/declaring-wires/declaring_wires.v (1108, 2023-01-09)
Basics/declaring-wires/declaring_wires.vcd (732, 2023-01-09)
Basics/declaring-wires/declaring_wires.vvp (4019, 2023-01-09)
Basics/declaring-wires/output.txt (354, 2023-01-09)
Basics/four-bit-comparator/ (0, 2023-01-09)
Basics/four-bit-comparator/a.out (2736, 2023-01-09)
Basics/four-bit-comparator/cascade_four_bit_comparator.v (671, 2023-01-09)
Basics/four-bit-comparator/four_bit_comparator.v (393, 2023-01-09)
Basics/four-bit-comparator/four_bit_comparator_.v (412, 2023-01-09)
Basics/four-bit-comparator/four_bit_comparator_.vvp (4995, 2023-01-09)
Basics/four-bit-comparator/tb_cascade_four_bit_comparator.v (773, 2023-01-09)
Basics/four-bit-comparator/tb_four_bit_comparator.v (668, 2023-01-09)
Basics/four-bit-comparator/tb_four_bit_comparator.vcd (750, 2023-01-09)
Basics/inverter/ (0, 2023-01-09)
Basics/inverter/Inverter.vcd (337, 2023-01-09)
Basics/inverter/inverter.v (381, 2023-01-09)
Basics/inverter/inverter.vvp (1919, 2023-01-09)
Basics/nor-gate/ (0, 2023-01-09)
Basics/nor-gate/nor-gate.v (1044, 2023-01-09)
Basics/nor-gate/nor-gate.vcd (400, 2023-01-09)
Basics/nor-gate/nor-gate.vvp (3087, 2023-01-09)
Basics/simple-and-gate/ (0, 2023-01-09)
Basics/simple-and-gate/.vcd (385, 2023-01-09)
Basics/simple-and-gate/output.txt (194, 2023-01-09)
Basics/simple-and-gate/simple_and_gate.v (1041, 2023-01-09)
Basics/simple-and-gate/simple_and_gate.v.vvp (2938, 2023-01-09)
Basics/simple-and-gate/simple_and_gate.vvp (2938, 2023-01-09)
Basics/xnor-gate/ (0, 2023-01-09)
Basics/xnor-gate/xnor-gate.v (1023, 2023-01-09)
Basics/xnor-gate/xnor-gate.vcd (392, 2023-01-09)
Basics/xnor-gate/xnor-gate.vvp (3074, 2023-01-09)
... ...
# Verilog
Simple verilog projects to learn verilog as well as testbench simulation.
These are all of my solutions to the problems on the [HDLBits](https://hdlbits.01xz.net/) site.
I am using Icarus Verilog for these projects and using GTKWave as the waveform viewer.
# Implemented gates with testbenches
#### Basics
* [XNOR Gate](https://github.com/berrios96sean/Verilog/tree/main/Basics/xnor-gate)
* [Simple AND Gate](https://github.com/berrios96sean/Verilog/tree/main/Basics/simple-and-gate)
* [NOR Gate](https://github.com/berrios96sean/Verilog/tree/main/Basics/nor-gate)
* [Inverter](https://github.com/berrios96sean/Verilog/tree/main/Basics/inverter)
* [Four Bit Comparator](https://github.com/berrios96sean/Verilog/tree/main/Basics/four-bit-comparator)
* [Declaring Wires](https://github.com/berrios96sean/Verilog/tree/main/Basics/declaring-wires)
* [7458 Chip](https://github.com/berrios96sean/Verilog/tree/main/Basics/7458-Chip)
#### Vectors
* [Simple Vector](https://github.com/berrios96sean/Verilog/tree/main/Vectors/simple-vector)
* [Half Word Splitter](https://github.com/berrios96sean/Verilog/tree/main/Vectors/half_word_splitter)
* [Bit Vector Reversal](https://github.com/berrios96sean/Verilog/tree/main/Vectors/bit-vector-reversal)
* [Bitwise Logical Operators](https://github.com/berrios96sean/Verilog/tree/main/Vectors/bitwise-logical-operators)
* [Four Input Gates](https://github.com/berrios96sean/Verilog/tree/main/Vectors/four-input-gates)
* [Vector Concatenation](https://github.com/berrios96sean/Verilog/tree/main/Vectors/vector-concatenation)
* [Vector Reversal](https://github.com/berrios96sean/Verilog/tree/main/Vectors/vector-reversal)
* [Replication Operator](https://github.com/berrios96sean/Verilog/tree/main/Vectors/replication-operator)
* [More Replication](https://github.com/berrios96sean/Verilog/tree/main/Vectors/more-replication)
#### Module Hierarchy
* [Module Within Module](https://github.com/berrios96sean/Verilog/tree/main/Module-hierarchy/using-module-within-module)
* [Connecting Ports By Position](https://github.com/berrios96sean/Verilog/tree/main/Module-hierarchy/connect-ports-by-position)
* [Connecting Ports By Name](https://github.com/berrios96sean/Verilog/tree/main/Module-hierarchy/connect-ports-by-name)
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