VLSI-Design-Project
所属分类：硬件设计
开发工具：Assembly
文件大小：0KB
下载次数：0
上传日期：2011-01-26 07:23:46
上 传 者：
sh-1993
说明： 实现IEEE 1149.1标准的JTAG控制器，
(JTAG controller implementing the IEEE 1149.1 standard,)
文件列表:
Deadline1/ (0, 2011-01-25)
Deadline1/JTAG_All.xlsx (8786, 2011-01-25)
Deadline1/JTAG_TAP.PNG (106115, 2011-01-25)
Deadline1/JTAG_TB.png (58091, 2011-01-25)
Deadline1/ModelSim/ (0, 2011-01-25)
Deadline1/ModelSim/Deadline1.cr.mti (551, 2011-01-25)
Deadline1/ModelSim/Deadline1.mpf (66264, 2011-01-25)
Deadline1/ModelSim/transcript (1804, 2011-01-25)
Deadline1/ModelSim/vsim.wlf (32768, 2011-01-25)
Deadline1/ModelSim/work/ (0, 2011-01-25)
Deadline1/ModelSim/work/_info (687, 2011-01-25)
Deadline1/ModelSim/work/_vmake (26, 2011-01-25)
Deadline1/ModelSim/work/tap/ (0, 2011-01-25)
Deadline1/ModelSim/work/tap/_primary.dat (2172, 2011-01-25)
Deadline1/ModelSim/work/tap/_primary.dbs (9310, 2011-01-25)
Deadline1/ModelSim/work/tap/_primary.vhd (1306, 2011-01-25)
Deadline1/ModelSim/work/tap/verilog.asm (29944, 2011-01-25)
Deadline1/ModelSim/work/tap/verilog.rw (6021, 2011-01-25)
Deadline1/ModelSim/work/tap_tb/ (0, 2011-01-25)
Deadline1/ModelSim/work/tap_tb/_primary.dat (1792, 2011-01-25)
Deadline1/ModelSim/work/tap_tb/_primary.dbs (5957, 2011-01-25)
Deadline1/ModelSim/work/tap_tb/_primary.vhd (72, 2011-01-25)
Deadline1/ModelSim/work/tap_tb/verilog.asm (11272, 2011-01-25)
Deadline1/ModelSim/work/tap_tb/verilog.rw (2401, 2011-01-25)
Deadline1/Test Bench Documentation.xlsx (15508, 2011-01-25)
Deadline1/Waveform.PNG (78896, 2011-01-25)
Deadline1/project.v (1741, 2011-01-25)
Deadline1/project_tb.v (863, 2011-01-25)
Deadline1/registers.v (2423, 2011-01-25)
Deadline1/report.docx (331933, 2011-01-25)
Deadline1/tap.v (3348, 2011-01-25)
Deadline1/tap_tb.v (2484, 2011-01-25)
Deadline1/utility.v (839, 2011-01-25)
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