cessor-Without-Interlocked-Pipeline-Stages-8-bit-
所属分类：硬件设计
开发工具：Verilog
文件大小：0KB
下载次数：0
上传日期：2019-04-30 07:31:35
上 传 者：
sh-1993
说明： 该项目旨在逐块设计和编码微处理器，然后在现场可编程门阵列（FPGA）板上运行。...，
(This project was aiming to design and code a Microprocessor block by block and then run it on a Field Programmable Gate Array (FPGA) Board. 8-bit Microprocessor was designed which consisted of Arithmetic Logical Unit (ALU) which can do all necessary mathematical operations. Moreover, measures to prevent hazards and problems were kept in mind.)
文件列表:
Data_Memory/ (0, 2019-04-30)
Data_Memory/Data_Mem.v (1221, 2019-04-30)
Data_Memory/Data_Mem_tb.v (2422, 2019-04-30)
Dependency_Check_Block/ (0, 2019-04-30)
Dependency_Check_Block/Dependency_Check_Block.v (5531, 2019-04-30)
Dependency_Check_Block/tb.v (1900, 2019-04-30)
Execution_Block/ (0, 2019-04-30)
Execution_Block/Execution_block.v (4664, 2019-04-30)
Jump_Control_Block/ (0, 2019-04-30)
Jump_Control_Block/Jump_Control_Block.v (2539, 2019-04-30)
PC_IM/ (0, 2019-04-30)
PC_IM/PC_IM.v (1926, 2019-04-30)
PC_IM/PC_IM_tb.v (2651, 2019-04-30)
PC_IM/add_sub_8bit.v (1280, 2019-04-30)
PC_IM/full_adder.v (669, 2019-04-30)
Register_Bank/ (0, 2019-04-30)
Register_Bank/Register_Bank.v (1345, 2019-04-30)
Register_Bank/Register_Bank_tb.v (2359, 2019-04-30)
Stall_Control/ (0, 2019-04-30)
Stall_Control/Stall_Control_Block.v (1378, 2019-04-30)
Stall_Control/Stall_Control_Block_tb.v (1428, 2019-04-30)
Top_Processor_Module.v (1911, 2019-04-30)
Top_Processor_Module_tb.v (1626, 2019-04-30)
Write_Back/ (0, 2019-04-30)
Write_Back/Write_Back_Block.v (764, 2019-04-30)
top_processor_module.bit (3825911, 2019-04-30)
# Microprocessor-Without-Interlocked-Pipeline-Stages-8-bit-
This project was aiming to design and code a Microprocessor block by block and then run it on a Field Programmable Gate Array (FPGA) Board. 8-bit Microprocessor was designed which consisted of Arithmetic Logical Unit (ALU) which can do all necessary mathematical operations. Moreover, measures to prevent hazards and problems were kept in mind.
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