10-gigabit-ethernet-mac-verification
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：0KB
下载次数：0
上传日期：2017-05-08 01:37:26
上 传 者：
sh-1993
说明： 使用SystemVerilog OOP测试台验证万兆以太网MAC，
(Verification of a 10 Gigabit Ethernet MAC using a SystemVerilog OOP Testbench,)
文件列表:
classes/ (0, 2017-05-07)
classes/coverage.sv (672, 2017-05-07)
classes/driver.sv (1948, 2017-05-07)
classes/environment.sv (1260, 2017-05-07)
classes/monitor.sv (2531, 2017-05-07)
classes/packet.sv (2721, 2017-05-07)
classes/scoreboard.sv (2837, 2017-05-07)
interface/ (0, 2017-05-07)
interface/xge_mac_interface.sv (2018, 2017-05-07)
sim/ (0, 2017-05-07)
sim/clean (89, 2017-05-07)
sim/runsim (376, 2017-05-07)
testbench/ (0, 2017-05-07)
testbench/tb_xge_mac.sv (3031, 2017-05-07)
testcases/ (0, 2017-05-07)
testcases/main/ (0, 2017-05-07)
testcases/main/testcase.sv (457, 2017-05-07)
testcases/oversize_packet/ (0, 2017-05-07)
testcases/oversize_packet/testcase.sv (458, 2017-05-07)
testcases/undersize_packet/ (0, 2017-05-07)
testcases/undersize_packet/testcase.sv (459, 2017-05-07)
# 10-gigabit-ethernet-mac-verification
Verification of a 10 Gigabit Ethernet MAC using a SystemVerilog OOP Testbench
This SystemVerilog OOP testbench verifies a 10 Gigabit Ethernet MAC that is written in Verilog RTL. The code for the RTL can be found at https://opencores.org/project,xge_mac.
Place the source code in the folders called in sim/runsim. Compile the code using Synopsys VCS.
近期下载者：
相关文件：
收藏者：