ALU-Verification-using-SystemVerilog
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：0KB
下载次数：0
上传日期：2023-03-04 07:35:45
上 传 者：
sh-1993
说明： 为ALU构建SystemVerilog环境，使用OOP测试台组件作为；刺激发生器，驱动器，监视器，记分板。ALU是...，
(Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was verified using QuestaSim.)
文件列表:
alu.v (3108, 2023-03-03)
alu_if.sv (521, 2023-03-03)
driver.svh (947, 2023-03-03)
env_pkg.sv (185, 2023-03-03)
monitor.svh (993, 2023-03-03)
packet.svh (378, 2023-03-03)
scoreboard.svh (5195, 2023-03-03)
stimulus_gen.svh (976, 2023-03-03)
testenv.svh (1078, 2023-03-03)
top.sv (1315, 2023-03-03)
# ALU-Verification-using-SystemVerilog
Build a SystemVerilog Environment for an ALU, including all OOP Testbench components as; stimulus generator, driver, monitor, scoreboard. RTL and TB was tested using QuestaSim.
ALU Block Diagram:
ALU Specifications:
ALU Testbench Architecture:
Project Workings:
after including the SV files in a project, and simulating the top module, the tb automatically prints out the bugs/mismatches between RTL and tb in a file within the same directory of the project, called "bugs.txt".
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