Ethernet-packet-Loopback-design-verification
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：0KB
下载次数：0
上传日期：2017-10-07 23:07:25
上 传 者：
sh-1993
说明： 使用SystemVerilog进行以太网分组环回设计验证，
(Ethernet packet loopback design verification using SystemVerilog,)
文件列表:
eth_bfm.sv (1703, 2017-10-07)
eth_config.sv (321, 2017-10-07)
eth_cov.sv (2197, 2017-10-07)
eth_dut.sv (1695, 2017-10-07)
eth_env.sv (459, 2017-10-07)
eth_gen.sv (2037, 2017-10-07)
eth_interface.sv (531, 2017-10-07)
eth_monitor.sv (1645, 2017-10-07)
eth_pkt.sv (2855, 2017-10-07)
eth_ref.sv (1886, 2017-10-07)
eth_tb.sv (418, 2017-10-07)
top.sv (1230, 2017-10-07)
# Ethernet-packet-Loopback-design-verification
Ethernet packet loopback design verification using SystemVerilog
Developed a TB for verification of Ethernet packet loopback design. The TB generated different types of packets for verification. Developed a TB architecture comprising of reference design, checker and monitor components.
Functional coverage and code coverage were used as closing criteria.
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