uvm-generator

所属分类:硬件设计
开发工具:SystemVerilog
文件大小:0KB
下载次数:0
上传日期:2021-05-06 03:51:50
上 传 者sh-1993
说明:  uvm测试台发生器,
(uvm testbench generator,)

文件列表:
common/ (0, 2021-05-05)
common/define.sv (168, 2021-05-05)
common/tbcfg.json (405, 2021-05-05)
filelist/ (0, 2021-05-05)
filelist/filelist.f (0, 2021-05-05)
script/ (0, 2021-05-05)
script/create_new_tc.pl (767, 2021-05-05)
script/link_rtl.pl (213, 2021-05-05)
script/makefile (3966, 2021-05-05)
script/sim.pl (5688, 2021-05-05)
script/tb_gen.py (29960, 2021-05-05)
script/vcs_help.txt (57662, 2021-05-05)
script/verdi_help.txt (39356, 2021-05-05)
tb/ (0, 2021-05-05)
tb/my_agent.sv (4766, 2021-05-05)
tb/my_base_test.sv (5208, 2021-05-05)
tb/my_clock_model.sv (683, 2021-05-05)
tb/my_driver.sv (5109, 2021-05-05)
tb/my_env.sv (4806, 2021-05-05)
tb/my_interface.sv (553, 2021-05-05)
tb/my_monitor.sv (4946, 2021-05-05)
tb/my_reference_model.sv (4741, 2021-05-05)
tb/my_scoreboard.sv (4653, 2021-05-05)
tb/my_sequencer.sv (4032, 2021-05-05)
tb/my_subscriber.sv (4790, 2021-05-05)
tb/my_tb_config.sv (1319, 2021-05-05)
tb/my_top.sv (1312, 2021-05-05)
tb/my_transaction.sv (1341, 2021-05-05)
tb/my_virtual_sequencer.sv (4568, 2021-05-05)
tc/ (0, 2021-05-05)
tc/my_case1/ (0, 2021-05-05)
tc/my_case1/my_case1.cfg (282, 2021-05-05)
tc/my_case1/my_case1.sv (6554, 2021-05-05)

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