simple_uvm_example
所属分类：硬件设计
开发工具：SystemVerilog
文件大小：0KB
下载次数：0
上传日期：2019-04-19 20:34:23
上 传 者：
sh-1993
说明： UVM测试台的基本示例，具有简单的序列、驱动程序、监视器、检查器和测试。，
(A basic example of a UVM testbench with a simple sequences, driver, monitor, checker, and test.,)
文件列表:
simple_uvm_example.sv (8524, 2019-04-19)
vcs_run (362, 2019-04-19)
# simple_uvm_example
A simple example of a UVM test environment, all in one file.
Includes:
* a simple DUT (a flip-flop)
* an interface shared as a virtual interface
* a driver, driven by a sequencer, sequences, and items
* a monitor that reports transactions through an analysis port
* a checker that checks transactions from an analysis port
* an environment object to instantiate and connect the test-bench components
* a uvm_test to instantiate the environment and run the sequences
* a top module to instantiate the DUT (device under test) and the interface
* a test selected from the command line with +UVM_TESTNAME
近期下载者：
相关文件：
收藏者：