l0mdt-hdl-design
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：0KB
下载次数：0
上传日期：2023-08-09 08:00:16
上 传 者：
sh-1993
说明： 为我们的学生和其他人克隆欧洲核子研究中心报告，
(Clone of CERN repo for our students and other people,)
文件列表:
l0mdt-hdl-design-devel/ (0, 2023-11-27)
l0mdt-hdl-design-devel/.before_script.yml (765, 2023-11-27)
l0mdt-hdl-design-devel/.devel_to_master.yml (604, 2023-11-27)
l0mdt-hdl-design-devel/.user_jobs.yml (11144, 2023-11-27)
l0mdt-hdl-design-devel/CODEOWNERS (396, 2023-11-27)
l0mdt-hdl-design-devel/HAL/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/fifo1KB_34bit/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/fifo1KB_34bit/fifo1KB_34bit.xci (50210, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/flx_link/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/flx_link/flx_link.xci (120929, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/flx_link_vio_0/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/flx_link_vio_0/flx_link_vio_0.xci (186603, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/flx_link_vio_1/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/flx_link_vio_1/flx_link_vio_1.xci (186624, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/framework_mmcm/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/framework_mmcm/framework_mmcm.xci (72694, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ila_0/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ila_0/ila_0.xci (694385, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ila_downlink/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ila_downlink/ila_downlink.xci (691516, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ila_lpgbt/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/ila_lpgbt/ila_lpgbt.xci (691844, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/mgt_10g24_gth/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/mgt_10g24_gth/mgt_10g24_gth.xci (122672, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/mgt_10g24_gty/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/mgt_10g24_gty/mgt_10g24_gty.xci (122518, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/onboardclk/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/ku15p/onboardclk/onboardclk.xci (72248, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/fifo1KB_34bit/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/fifo1KB_34bit/fifo1KB_34bit.xci (50210, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/flx_link/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/flx_link/flx_link.xci (120937, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/flx_link_vio_0/ (0, 2023-11-27)
l0mdt-hdl-design-devel/HAL/IP/vu13p/flx_link_vio_0/flx_link_vio_0.xci (186640, 2023-11-27)
... ...
# l0mdt-hdl-design
This repository holds all the FPGA design for the L0MDT (MDTTP) project. It
uses the Hog framework, which allows multiple top files and automated building.
This repository is expected to have a mix of HDL approaches: VDHL, Verilog (and
family), HLS
**See Wiki area for other information**
## How to retrieve the code
`git clone --recurse-submodules ssh://git@gitlab.cern.ch:7999/atlas-tdaq-phase2-l0mdt-electronics/l0mdt-fpga-design.git`
## Directory structure
Hog dictates the basic directory structure, please see [this](https://cern.ch/Hog).
Full chain projects are stored in the `Top/l0mdt*` folders. The Hog and AXI configuration files for these projects are automatically generated using the `Top/generate_mdt_flavors.tcl` script. This uses the `Top/base_l0mdt` project as a template and creates the selected projects, according to the parameters declared in the `Top/mdt_flavors.yml` file.
For example, the configuration,
```yaml
ku15p_lsf_upt:
fpga: xcku15p-ffva1760-2-e
board_pkg: board_pkg_mpi_ku15p
sf: lsf
pt: upt
constraints:
- "pinouts_mpi_ku15p.xdc"
variants:
default:
link_map: "link_map_ku15p"
sector_id: 3
sector_side: 0
endcap: 0
large: 0
en_neighbors: 0
en_daq: 1
hog_only_synth: 1
hog_no_bitstream: 1
zynq_target: 7s # 7s or usp
```
will create the `Top/l0mdt_ku15p_lsf_upt` project, with the configuration to create a firmware for the KU15P, with the LSF segment finder and the UPT momentum calculator modules.
To create a new `l0mdt` project, just add a new definition in the yaml file and run the `Make flavors` command. Each `l0mdt` project, contains also a unique AXI definition, which is defined in the `Top/project/slaves.yaml` and `Top/project/address_tables/address_apollo.xml` files. These files are currently copied from the `base_l0mdt` project, and can be modified by the users to adapt for their needs. The `generate_mdt_flavors` script would check if these files already exist, and does not overwrite them, to avoid loss of work. For the future, we plan to generate also the `slaves.yaml` and the `address_apollo.xml` files automatically from the `mdt_flavors.yml`.
When generating the project configurations, the tool also parses the `slaves.yaml` file to create the correspondent `top_control.vhd` and `top_l0mdt.vhd` files, which are stored in the `Top/project/` folder. When creating the project for the first time, please remember to commit also these files to git, otherwise the CI would fail.
If you modify the `slaves.yaml` in a project, you can automatically update the `top_*` files by launching the following command from the main path of the repository.
```shell
./Top/update_top_modules.tcl
```
## GitLab workflow
- Issues created to track changes in code, branches created from issues.
- Master branch protected to hold stable (release) versions
- Devel branch to concentrate all the merges before release
- Working branches created as needed
- feature-\: for features implementation
- hotfix-\: for fixes directly on master and devel branches.
Please see: [A successful git branching model](https://nvie.com/posts/a-successful-git-branching-model/)
## Hog documentation hub
http://hog-user-docs.web.cern.ch/
## Some instructions to simulate and implement the code
.... TBD
## Gitlab CI
... TBD
近期下载者：
相关文件：
收藏者：