HDLParserSharp
所属分类：VHDL/FPGA/Verilog
开发工具：C#
文件大小：0KB
下载次数：0
上传日期：2023-04-23 05:55:14
上 传 者：
sh-1993
说明： 用C#（hdlConvertor的C#实现）编写的硬件描述语言（HDL）解析器，
(Hardware description language (HDL) parser wrote in C# (C# implemetation of hdlConvertor),)
文件列表:
LICENSE (26526, 2023-04-22)
grammars/ (0, 2023-04-22)
grammars/SystemVerilog2017/ (0, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017Lexer.cs (119223, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017Lexer.interp (132733, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017Lexer.tokens (9640, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017Parser.cs (1871143, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017Parser.interp (287176, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017Parser.tokens (9887, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017ParserBaseListener.cs (386324, 2023-04-22)
grammars/SystemVerilog2017/SystemVerilog2017ParserListener.cs (302743, 2023-04-22)
grammars/SystemVerilog2017Lexer.g4 (11847, 2023-04-22)
grammars/SystemVerilog2017Parser.g4 (75606, 2023-04-22)
grammars/VHDL/ (0, 2023-04-22)
grammars/VHDL/VHDLLexer.cs (48465, 2023-04-22)
grammars/VHDL/VHDLLexer.interp (52723, 2023-04-22)
grammars/VHDL/VHDLLexer.tokens (2411, 2023-04-22)
grammars/VHDL/VHDLParser.cs (728802, 2023-04-22)
grammars/VHDL/VHDLParser.interp (101713, 2023-04-22)
grammars/VHDL/VHDLParser.tokens (2411, 2023-04-22)
grammars/VHDL/VHDLParserBaseListener.cs (172130, 2023-04-22)
grammars/VHDL/VHDLParserListener.cs (131682, 2023-04-22)
grammars/VHDLLexer.g4 (6924, 2023-04-22)
grammars/VHDLParser.g4 (28445, 2023-04-22)
grammars/antlr-4.12.0-complete.jar (3433952, 2023-04-22)
grammars/antlr-4.9-complete.jar (2100306, 2023-04-22)
grammars/verilogPreprocLexer.g4 (13333, 2023-04-22)
grammars/verilogPreprocParser.g4 (3762, 2023-04-22)
solution/ (0, 2023-04-22)
solution/HDLParserSharp/ (0, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/ (0, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/BasicUnit/ (0, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/BasicUnit/IAttributed.cs (307, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/BasicUnit/ICodePosition.cs (388, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/BasicUnit/ICoded.cs (289, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/BasicUnit/IDocumented.cs (224, 2023-04-22)
solution/HDLParserSharp/HDLAbstractSyntaxTree/BasicUnit/INamed.cs (255, 2023-04-22)
... ...
# HDLParserSharp
## Introduction
HDLParser# is a hardware description language (HDL) parser wrote in C#.
Basiclly, the core of language processing unit of the HDLParser# is C# implemetation of hdlConvertor.
With the ANTLR4 C# library, we use the Lexer and Parser files in hdlConvertor to generate the C# library of HDLLexer and HDLParser.
And, we construct a C# class for ASTs, using many modern and efficiency C# language features.
Then, we re-write the parser library in C# to generate the ANTLR4 objects to the AST.
## The hdlConvertor library
The [Nic30/hdlConvertor](https://github.com/Nic30/hdlConvertor) is a System Verilog and VHDL parser library (MIT License),
which contains
* ANTLR4 generated VHDL/(System) Verilog parser with full language support;
* Convertors from raw VHDL/SV AST to universal HDL AST;
* Convertors from this HDL AST to SV/VHDL/JSON and other formats;
* Compiler focused utils for manipulation with HDL AST.
## Why we do this work
The C# is a very modern and efficiency OOP language, contains many useful attributes and features to make programming easily.
The libraries of C# is also very rich, such as System.Linq can help you use simple query sentence to query the enumerable data.
We'd like to apply these features for HDL parser then we can construct many HDL applications by C#, such as Linter and BlockDesigner.
## What we plan to do?
We plan to reproduce the work of hdlConvertor completely and try to add new features to it (Such as the interface in SystemVerilog is unsupported now in hdlConverter).
And, we plan to use Lua (or some script languages, like Python) to evaluate some expressions in the AST, then we can get some result in "synthesis-time".
Finally, we plan to write a BlockDesigner in C# like the Xilinx Block Design, it can make we connect wires and buses easily when we design the top or high-level entries.
近期下载者：
相关文件：
收藏者：