1-D-Time-Domain-Convolution-on-FPGA
所属分类：驱动编程
开发工具：VHDL
文件大小：0KB
下载次数：0
上传日期：2022-02-11 03:43:17
上 传 者：
sh-1993
说明： 在本项目中，FPGA被编程为使用VHDL执行一维时域卷积。它由两个主要部分组成，将由......、...，
(In this project a FPGA is programmed to perform 1-D time domain convolution using VHDL. It consists of two major parts to be completed which were the DMA interface between memory(DRAM) and the user_app and the design oof the signal and kernel buffers to perform convolution.)
文件列表:
1-D time domain convolution.pdf (4157138, 2022-02-10)
dma/ (0, 2022-02-10)
dma/accelerator_1.0/ (0, 2022-02-10)
dma/accelerator_1.0/bd/ (0, 2022-02-10)
dma/accelerator_1.0/bd/bd.tcl (7749, 2022-02-10)
dma/accelerator_1.0/component.xml (55988, 2022-02-10)
dma/accelerator_1.0/drivers/ (0, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/ (0, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/data/ (0, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/data/accelerator.mdd (188, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/data/accelerator.tcl (168, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/src/ (0, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/src/Makefile (454, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/src/accelerator.c (184, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/src/accelerator.h (2451, 2022-02-10)
dma/accelerator_1.0/drivers/accelerator_v1_0/src/accelerator_selftest.c (1954, 2022-02-10)
dma/accelerator_1.0/example_designs/ (0, 2022-02-10)
dma/accelerator_1.0/example_designs/bfm_design/ (0, 2022-02-10)
dma/accelerator_1.0/example_designs/bfm_design/accelerator_v1_0_tb.v (6808, 2022-02-10)
dma/accelerator_1.0/example_designs/bfm_design/design.tcl (3780, 2022-02-10)
dma/accelerator_1.0/example_designs/debug_hw_design/ (0, 2022-02-10)
dma/accelerator_1.0/example_designs/debug_hw_design/accelerator_v1_0_hw_test.tcl (1361, 2022-02-10)
dma/accelerator_1.0/example_designs/debug_hw_design/design.tcl (8301, 2022-02-10)
dma/accelerator_1.0/hdl/ (0, 2022-02-10)
dma/accelerator_1.0/hdl/accelerator_v1_0.vhd (4922, 2022-02-10)
dma/accelerator_1.0/hdl/accelerator_v1_0_S00_AXI.vhd (13980, 2022-02-10)
dma/accelerator_1.0/src/ (0, 2022-02-10)
dma/accelerator_1.0/src/AND.vhd (768, 2022-02-10)
dma/accelerator_1.0/src/NOT.vhd (639, 2022-02-10)
dma/accelerator_1.0/src/REGISTER.vhd (964, 2022-02-10)
dma/accelerator_1.0/src/address_generator.vhd (2807, 2022-02-10)
dma/accelerator_1.0/src/config_pkg.vhd (1508, 2022-02-10)
dma/accelerator_1.0/src/counter.vhd (2783, 2022-02-10)
dma/accelerator_1.0/src/ctrl.vhd (2143, 2022-02-10)
dma/accelerator_1.0/src/delay.vhd (2175, 2022-02-10)
dma/accelerator_1.0/src/dram_cores/ (0, 2022-02-10)
dma/accelerator_1.0/src/dram_cores/dram_rd_ram0.edn (808132, 2022-02-10)
dma/accelerator_1.0/src/dram_cores/dram_rd_ram0_0_funcsim.vhdl (307552, 2022-02-10)
dma/accelerator_1.0/src/dram_cores/dram_rd_ram1.edn (815733, 2022-02-10)
... ...
# 1-D-Time-Domain-Convolution-on-FPGA
In this project a FPGA is programmed to perform 1-D time domain convolution using VHDL. It consists of two major parts to be completed which were the DMA interface between memory(DRAM) and the user_app and the design oof the signal and kernel buffers to perform convolution.
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