文件列表:

Initial program/ (0, 2023-10-04)
Initial program/blink.v (1297, 2023-10-04)
Problem set 1/ (0, 2023-10-04)
Problem set 1/ALU.v (2621, 2023-10-04)
Problem set 1/ALU_TCL-file.txt (575, 2023-10-04)
Problem set 1/Nexys-4-DDR-Master.xdc (19709, 2023-10-04)
Problem set 1/subtractor.v (1371, 2023-10-04)
Problem set 1/subtractor_TCL-file.txt (342, 2023-10-04)
Problem set 2/ (0, 2023-10-04)
Problem set 2/Nexys-4-DDR-Master.xdc (19586, 2023-10-04)
Problem set 2/Package_Sorter.v (6783, 2023-10-04)
Problem set 2/TrafficLightController.v (3470, 2023-10-04)

# VerilogPrograms This repository catalogs my programming journey with the Hardware Description Langauge (HDL) Verilog. All work was done with the Nexys A7 FPGA Trainer Board and the Vivado Design Suite **Guide** Initial program - Simply a blinking light on LED 0. Blinky is generally the starter program in hardware stuff. Comparable to "Hello, World!" in a general language like C. **Problem Set 1:** Subtractor - A 1-bit full subtractor described using logic functions derived from a truth table for a full subtractor. A second module is included which instantiates 4 of the single-bit subtractors and creates a 4-bit subtractor. Associated TCL commands are given for testing cases. ALU - An 8-function arithmetic Logic Unit is described using case statements, assigning the proper output, and carrying out where necessary. Subtractor on a physical FPGA - An XDC constraints file is given corresponding to assignments to switches and LEDs. The code is the same as the subtractor.v file. **Problem Set 2:** Package sorter - A package sorter that classifies packages based on different criteria as well as their weights. A test-bench is given along with the source code testing an input sequence of weights Traffic light controller - Traffic light controller that has an A street, B street, and a pedestrian crosswalk.

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