ProgrammableFIRASIC
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开发工具：Verilog
文件大小：0KB
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上传日期：2020-01-10 01:58:02
上 传 者：
sh-1993
说明： 可编程FIR滤波器ASIC，
(Programmable FIR Filter ASIC,)
文件列表:
CNTRL.v (25231, 2020-01-09)
CNTRL_SIM.v (1464, 2020-01-09)
FIR_PPT_brunogracia2.pdf (815573, 2020-01-09)
brunogracia_FIR_final_project_report.pdf (1397253, 2020-01-09)
filter_memory.mem (14, 2020-01-09)
signal_memory.mem (23, 2020-01-09)
# Programmable Finite Impulse Response Filter ASIC
A 45nm implementation with two embedded ROMs for programming the taps of the Finite Impulse Response filter. Cadence and Synopsys EDA tools used.
Designed in Verilog at RTL, and simulated for desired operation using Xilinx Vivado.
# Contents
Please refer to the report for power, timing, and area analyses between technology nodes 45, 90, and 180 nm.
Single CNTRL.v verilog file attached consists of all modules into one file for use with RTL Compilers.
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