文件列表:

FPGA_Project.pdf (2820010, 2023-09-25)
FPGA_handin_YongLI_MarcZHAN.zip (206161, 2023-09-25)
Porject_FPGA_IP/ (0, 2023-09-25)
Porject_FPGA_IP/.DS_Store (10244, 2023-09-25)
Porject_FPGA_IP/FPGA/ (0, 2023-09-25)
Porject_FPGA_IP/FPGA/.DS_Store (10244, 2023-09-25)
Porject_FPGA_IP/FPGA/Compteur_Tempo.vhd (3251, 2023-09-25)
Porject_FPGA_IP/FPGA/DCC_Bit0.vhd (4085, 2023-09-25)
Porject_FPGA_IP/FPGA/DCC_Bit1.vhd (4082, 2023-09-25)
Porject_FPGA_IP/FPGA/DCC_Compteur.vhd (1729, 2023-09-25)
Porject_FPGA_IP/FPGA/DDC_MAE.vhd (4230, 2023-09-25)
Porject_FPGA_IP/FPGA/Diviseur_Horloge.vhd (1534, 2023-09-25)
Porject_FPGA_IP/FPGA/MAE.vhd (10078, 2023-09-25)
Porject_FPGA_IP/FPGA/MAE_Compteur.vhd (1727, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/ (0, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/.DS_Store (6148, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Compteur_Tempo.vhd (3251, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/DCC_Bit0.vhd (4085, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/DCC_Bit1.vhd (4082, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/DCC_Compteur.vhd (1729, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/DCC_wrapper.xsa (135911, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/DDC_MAE.vhd (4230, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Diviseur_Horloge.vhd (1534, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/MAE.vhd (10078, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/MAE_Compteur.vhd (1727, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ (0, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/ (0, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/ (0, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/ (0, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/0261aa1d5cbfd682.xci (5874, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/DCC_axi_gpio_0_1.dcp (70513, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/DCC_axi_gpio_0_1_sim_netlist.v (92966, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/DCC_axi_gpio_0_1_sim_netlist.vhdl (111581, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/DCC_axi_gpio_0_1_stub.v (2362, 2023-09-25)
Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0261aa1d5cbfd682/DCC_axi_gpio_0_1_stub.vhdl (2516, 2023-09-25)
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Porject_FPGA_IP/FPGA/Project_FPGA/Project_FPGA.cache/ip/2020.2/0717d7a2068e85a1/DCC_microblaze_0_axi_intc_0.dcp (103406, 2023-09-25)
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# FPGA1 Course - DCC(Digital Command Control) Central Project This course, taught by Professor Julien Denoulet at LIP6, provides an exciting opportunity to dive into the world of Field-Programmable Gate Arrays (FPGAs). The associated TP (Travaux Pratiques) classes are conducted by Amine Rhouni. Throughout this course, we've gained valuable insights and hands-on experience in FPGA development, with a special focus on our intriguing train control project. ## About this Git Repository Welcome to the FPGA1 Course - Train Control Project Git repository! The primary purpose of this repository is to provide a comprehensive overview of our work throughout the TP (Travaux Pratiques) classes, with a particular focus on the second part of our project. Here's what you can expect to find in this repository: ## Orgnization of TPs The Tp classes are mainly in two parts - Part 1 (Foundations with Vivado and Vitis): In the initial part of the course, we'll familiarize ourselves with essential tools like Vivado and Vitis. These tools are the building blocks of FPGA development and will equip us with the necessary skills to tackle the project in the second part. - Part 2 (The Train Control Project): In the second part of the course, we'll put our knowledge into practice by working on the Train Control Project. Here, we'll design and implement a DCC system for a model train, bridging theory with hands-on experience to create a functional application. ## Installation VHDL Part (Hardware Design): __Vivado Installation:__ Ensure that you have Xilinx Vivado and vitis installed on your system. __Open Project in Vivado:__ - Launch Vivado. - Open the project by navigating to the project's top-level directory and selecting the project file (e.g., project_name.xpr). __Synthesize and Simulate:__ - Within Vivado, synthesize and simulate the VHDL design using the tools and features provided by Vivado. - Refer to Vivado's documentation or online resources for detailed instructions on synthesis and simulation. ## Git Repository Directory ``` MU4IN108-FPGA1 │ README.md │ FPGA_Project.pdf (Project Report) | FPGA_handin_YongLI_MarcZHAN.zip (Resources handed in) │ └───Porject_FPGA_IP(Second part of the project) | |... | └───Project_FPGA (First Part of the project) | |... | └───TP1-3 (First part of the TP classes) |... ``` ## Support - Email : liyongmb@gmail.com - Discord : lyyyds ## Conclusion The FPGA1 course, under the guidance of Professor Julien Denoulet and TP classes led by Amine Rhouni, promises a rewarding journey through the world of FPGA technology. The Train Control Project, in particular, will challenge and inspire you as you bring your FPGA skills to life in a real-world application.

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