Castlab-DMA
所属分类：VHDL/FPGA/Verilog
开发工具：SystemVerilog
文件大小：0KB
下载次数：1
上传日期：2023-10-18 16:08:42
上 传 者：
sh-1993
说明： Xilinx FPGA VCU118上的可系统化DMA单元，
(A systhesiable DMA unit on Xilinx FPGA VCU118,)
文件列表:
01_RTL/ (0, 2023-10-18)
01_RTL/APB_master.sv (3090, 2023-10-18)
01_RTL/DUT.sv (5682, 2023-10-18)
01_RTL/Sram.sv (2077, 2023-10-18)
01_RTL/command_gen.sv (73801, 2023-10-18)
01_RTL/dma_pkg.sv (413, 2023-10-18)
01_RTL/fpga_top.sv (4930, 2023-10-18)
02_TB/ (0, 2023-10-18)
02_TB/APB_master.sv (3090, 2023-10-18)
02_TB/TB_APB.sv (7840, 2023-10-18)
03_LIST/ (0, 2023-10-18)
03_LIST/vlist.f (300, 2023-10-18)
Lab2 instructions.txt (1774, 2023-10-18)
Lab2.pdf (380990, 2023-10-18)
dma_constrs.xdc (570, 2023-10-18)
mem0.coe (342, 2023-10-18)
mem0_init.mem (252, 2023-10-18)
mem1.coe (370, 2023-10-18)
mem1_init.mem (252, 2023-10-18)
shell.tcl (14438, 2023-10-18)
start_vivado.sh (38, 2023-10-18)
# Castlab-DMA
This project implement a Direct Memory Access unit on Xilinx FPGA VCU118
Please refer to the Lab2.pdf file for more description
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