1x3-Router-UVM-TestBench
所属分类：硬件设计
开发工具：SystemVerilog
文件大小：0KB
下载次数：0
上传日期：2023-10-29 00:16:31
上 传 者：
sh-1993
说明： 路由器UVM测试台
(Router UVM Testbench)
文件列表:
read_xtn.sv (1052, 2023-11-08)
router_env.sv (2967, 2023-11-08)
router_env_config.sv (662, 2023-11-08)
router_if.sv (1667, 2023-11-08)
router_pkg.sv (984, 2023-11-08)
router_rd_agent.sv (1399, 2023-11-08)
router_rd_agt_config.sv (472, 2023-11-08)
router_rd_agt_top.sv (1170, 2023-11-08)
router_rd_driver.sv (2100, 2023-11-08)
router_rd_monitor.sv (2129, 2023-11-08)
router_rd_seqs.sv (1607, 2023-11-08)
router_rd_sequencer.sv (344, 2023-11-08)
router_scoreboard.sv (5227, 2023-11-08)
router_test.sv (8406, 2023-11-08)
router_virtual_seqs.sv (7829, 2023-11-08)
router_virtual_sequencer.sv (934, 2023-11-08)
router_wr_agent.sv (1401, 2023-11-08)
router_wr_agent_config.sv (470, 2023-11-08)
router_wr_agt_top.sv (1175, 2023-11-08)
router_wr_driver.sv (2558, 2023-11-08)
router_wr_monitor.sv (2514, 2023-11-08)
router_wr_seqs.sv (3898, 2023-11-08)
router_wr_sequencer.sv (368, 2023-11-08)
top.sv (3293, 2023-11-08)
write_xtn.sv (2244, 2023-11-08)
# 1x3-Router-Design-and-UVM-TestBench
Router 1*3 Design Block Diagram
Router UVM Testbench:
#Router packet structure
#Router input protocol
#Router output protocol
Features to be verified:
1.Packet should reach all 3 destinations properly as per the channel address.
2.All 3 destinations should receive packet of all the possible payload lengths.
3.When the data is corrupted,error signal should go high.
4.When data out is not read within 30 cycles of valid out going high,soft reset should occur.
近期下载者：
相关文件：
收藏者：