XHDL4[1].0.40
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7489KB
下载次数：104
上传日期：2011-11-16 15:23:02
上 传 者：
树悠悠
说明： 实现VHDL和verilog之间的语言转换，方便程序之间的以致，XHDL版本4.0.40。
(Achieved between VHDL and verilog language conversion between programs so easy, XHDL version 4.0.40.)
文件列表:
XHDL4[1].0.40\XHDL4.0.40\bin\mingwm10.dll (15964, 2007-12-28)
XHDL4[1].0.40\XHDL4.0.40\bin\QtCore4.dll (2730496, 2009-06-25)
XHDL4[1].0.40\XHDL4.0.40\bin\QtGui4.dll (11266048, 2009-06-22)
XHDL4[1].0.40\XHDL4.0.40\bin\QtNetwork4.dll (1380352, 2009-06-22)
XHDL4[1].0.40\XHDL4.0.40\bin\xhdl.exe (3628544, 2010-03-08)
XHDL4[1].0.40\XHDL4.0.40\bin\xhdlc.exe (3616256, 2009-08-09)
XHDL4[1].0.40\XHDL4.0.40\docs\pdf\change_log.pdf (53898, 2009-08-09)
XHDL4[1].0.40\XHDL4.0.40\docs\pdf\X-HDL.pdf (1430984, 2009-08-09)
XHDL4[1].0.40\XHDL4.0.40\docs\pdf\XLM.pdf (131184, 2009-07-01)
XHDL4[1].0.40\XHDL4.0.40\packages\non_synthesizable\XHDL_bit.vhdl (14108, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\packages\non_synthesizable\XHDL_misc.vhdl (3586, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\packages\non_synthesizable\XHDL_std_logic.vhdl (15382, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\packages\non_synthesizable\XHDL_std_ulogic.vhdl (16038, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\packages\synthesizable\XHDL_bit.vhdl (9408, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\packages\synthesizable\XHDL_std_logic.vhdl (10453, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\packages\synthesizable\XHDL_std_ulogic.vhdl (10594, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\util\make_lib.pl (7362, 2009-06-26)
XHDL4[1].0.40\XHDL4.0.40\docs\pdf (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\packages\non_synthesizable (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\packages\synthesizable (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\bin (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\docs (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\license (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\packages (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40\util (0, 2011-11-01)
XHDL4[1].0.40\XHDL4.0.40 (0, 2011-11-01)
XHDL4[1].0.40 (0, 2011-11-01)
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