mips-assembler
所属分类:嵌入式/单片机/硬件编程
开发工具:Rust
文件大小:0KB
下载次数:0
上传日期:2023-11-23 04:58:22
上 传 者:
sh-1993
说明: mips汇编程序
(mips assembler)
文件列表:
Cargo.toml (183, 2023-12-08)
img/ (0, 2023-12-08)
img/demo.png (491322, 2023-12-08)
src/ (0, 2023-12-08)
src/instruction.rs (5863, 2023-12-08)
src/main.rs (1414, 2023-12-08)
src/parser.rs (11814, 2023-12-08)
testcase/ (0, 2023-12-08)
testcase/factorial6.s (417, 2023-12-08)
testcase/if0.s (3000, 2023-12-08)
testcase/test.s (415, 2023-12-08)
# MIPS Assembler
![demo image](https://github.com/cho0h5/mips-assembler/blob/master/img/demo.png)
# Build and Execute
## Prerequirement
- Rust (https://www.rust-lang.org/learn/get-started)
```sh
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
```
## Build
```sh
git clone https://github.com/cho0h5/mips-assembler.git
cd mips-assembler
cargo build --release
mv target/release/mips-assembler .
```
## Execute
```sh
./mips-assembler testcase/factorial6.s
```
Then, you can generate factorial6.bin!
## Run binary code
Go to https://github.com/cho0h5/mips-simulator
# Grammer
```
PROGRAM -> LINE PROGRAM |
LINE -> LABEL : CODE | CODE
CODE -> R | I | J
R ->
add REG REG REG |
addu REG REG REG |
and REG REG REG |
jr REG |
nor REG REG REG |
or REG REG REG |
slt REG REG REG |
sltu REG REG REG |
sll REG REG IMM5 |
srl REG REG IMM5 |
sub REG REG REG |
subu REG REG REG |
div REG REG |
divu REG REG |
mfhi REG |
mflo REG |
mult REG REG |
multu REG REG |
sra REG REG IMM5 |
syscall
I ->
addi REG REG IMM16 |
addiu REG REG IMM16 |
andi REG REG IMM16 |
beq REG REG LABEL |
bne REG REG LABEL |
lbu REG IMM16(REG) |
lhu REG IMM16(REG) |
lui REG IMM16 |
lw REG IMM16(REG) |
ori REG REG IMM16 |
slti REG REG IMM16 |
sltiu REG REG IMM16 |
sb REG IMM16(REG) |
sh REG IMM16(REG) |
sw REG IMM16(REG)
J ->
j LABEL |
jal LABEL
REG ->
$zero |
$at |
$v0 |
$v1 |
$a0 |
$a1 |
$a2 |
$a3 |
$t0 |
$t1 |
$t2 |
$t3 |
$t4 |
$t5 |
$t6 |
$t7 |
$s0 |
$s1 |
$s2 |
$s3 |
$s4 |
$s5 |
$s6 |
$s7 |
$t8 |
$t9 |
$k0 |
$k1 |
$gp |
$sp |
$fp |
$ra
IMM5 -> `5bit constant`
IMM16 -> `16bit constant`
LABEL -> `string`
```
## Example
```asm
addi $a0 $zero 6
jal fact
add $a0 $v0 $zero
addi $v0 $zero 1
syscall
addi $a0 $zero 10
addi $v0 $zero 11
syscall
addi $v0 $zero 10
syscall
fact: addi $sp $sp -8
sw $ra 4($sp)
sw $a0 0($sp)
slti $t0 $a0 1
beq $t0 $zero L1
addi $v0 $zero 1
addi $sp $sp 8
jr $ra
L1: addi $a0 $a0 -1
jal fact
lw $a0 0($sp)
lw $ra 4($sp)
addi $sp $sp 8
mult $v0 $a0
mflo $v0
jr $ra
```
## Authors
| Name | Student No. |
|---|---|
| | 20204946 |
| | 20203436 |
| | 20203458 |
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