Overview

This project simulates 8259A PIC behavior using verilog, PIC is short for Programmable Interrupt Controller. The design was inspired from the Intel datasheet with some modifications.

The design was divided into 4 major blocks as follows:

• Read Write logic block
• Control logic block
• Interrupt logic block
• Cascade logic block

Our lovely PIC 8259A is designed to be:

• 8086 compatible
• Programmable
• Single +5V supply, no master clock
• Eight-Level Priority Controller
• Expandable to 64 Levels via cascading
• Handling interrupts in fully-nested mode
• Interrupt masking compatible
• AEOI supportive
• supportive for reading status

Sequence of operation

1. All command words are sent from 8086 to the RW logic.
2. RW logic parses the command words sending flags to control logic
3. Whilst command words are being sent, all blocks are initializing according to the command words
4. Once all command words are sent, other blocks can start working on the interrupt.
5. Control logic triggers 8086 for interrupts
6. Interrupt starts upon recieving the first INTA(active low) pulse, fetching the IRs
7. Priority resolver chooses which request will be served taking into consideration various modes(fully-nested,rotation mode etc...)
8. Control logic puts the vector address(from ISR) on the data bus upon recieving the second INTA pulse only if addressWrite flag is high (in single mode), in case of cascade mode, depending on current interrupt location, it would be put on the data bus by one of the slaves.
9. 8086 sends read signal, allowing to read ISR(current interrupt request in service), IRR and IMR

Block diagrams

Control logic block diagram, the mastermind of the PIC, takes flags from R/W logic, parses the data to give it to other blocks



Read write logic block diagram, this block deals with 8086 directly, recieving command words, writing them and sending flags to the control logic to make all blocks initialize their states and work correctly



To serve an interrupt, you have to notice it first. Handling multiple interrupts at the same time determining which has the highest priority, that is part of the Interrupt Logic Module's job



Instead of just 8 devices connected to the PIC, we can extend that up to 64 devices using the Cascade Logic Module

Signals

Control Logic Signals (click on picture for better view)



R/W Logic Signals (click on picture for better view)



Cascade Logic Signals (click on picture for better view)



Cascade Logic Signals (click on picture for better view)

Simulation

PIC8259A Simulation

R/W Logic Simualtion

All command words written	ICW3 and ICW4 aren't written
ICW3 isn't written	ICW4 isn't written

Control Logic simulation

Interrupt Logic Simulation

Cascade Logic Simulation

Testbench methodolgy

• Initializing using command words (ICWs), testing all possible cases of missing ICW3 and ICW4, and their existence
• Writing command words
• Setting interrupt requests
• Testing fully nested mode
• Testing read status mode
• Testing AEOI

Modifications

• R/W logic works with an internal clock, since the command words need some form of sequence to operate, a clock was needed to enhance and ease the design of the logic of command words
• All blocks won't start working unless all command words are sent
• 8086 must send all OCWs to facilitate the design of the blocks
• RW logic takes some of the control logic tasks such as parsing the data for command words and sends them to contorl logic
• Control logic and R/W logic can be reduced to one single complex block
• Interrupt logic block recieves the acknowledgement (INTA) directly from 8086
• Control logic sets the 8 bit vector address on the data bus not the ISR
• Control logic is responsible for reading the status of PIC, in exchange of R/W logic parsing the data and setting flags.

Team members

Name	ID	GitHub username	Contribution
Abdullah Mohammed	2001803	AntiHexCode	Control Logic, Read Logic, PIC8259A, Cascade Logic, Interrupt Logic
Ahmad Mahfouz	2002238	rye141200	Write Logic,Control logic, PIC8259A, Report
Mohammed Mostafa	2001299	mohamed-most	Interrupt Logic, Report