digital-alarm-clock-vhdl
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：0KB
下载次数：1
上传日期：2024-01-12 07:47:15
上 传 者：
sh-1993
说明： 该VHDL项目使用Xilinx Vivado在FPGA上实现了数字闹钟。该项目包括时钟生成组件…
(This VHDL project implements a digital alarm clock on an FPGA using Xilinx Vivado. The project includes components for clock generation, …)
文件列表:
50mhz_clock_frequency.vhd
LICENSE
digital_alarm_clock.vhd
# Digital Alarm Clock VHDL Project
This VHDL project implements a digital alarm clock on an FPGA using Xilinx Vivado. The project includes components for clock generation, timekeeping, display control, and alarm logic. The clock supports user inputs for setting the alarm, and the alarm can be snoozed.
## Features
- Clock generation with 1Hz frequency
- Timekeeping in HH:MM:SS format
- User-friendly alarm setting
- Snooze functionality
- Display control for custom configurations
## Table of Contents
- [How to Use](https://github.com/niladrigithub/digital-alarm-clock-vhdl/blob/master/#how-to-use)
- [Contributing](https://github.com/niladrigithub/digital-alarm-clock-vhdl/blob/master/#contributing)
- [License](https://github.com/niladrigithub/digital-alarm-clock-vhdl/blob/master/#license)
## How to Use
1. Clone the repository.
```bash
git clone https://github.com/niladrigithub/Digital-Alarm-Clock-VHDL.git
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