Intro-Logic-Design
所属分类：硬件设计
开发工具：Verilog
文件大小：0KB
下载次数：0
上传日期：2024-01-18 22:22:39
上 传 者：
sh-1993
说明： 在Basys 3 Artix-7 FPGA训练板上利用Verilog编程为CSE 100 Logic Design类完成的实验室工作
(Lab work done for CSE 100 Logic Design class utilizing Verilog programing on a Basys 3 Artix-7 FPGA Trainer Board)
文件列表:
Flappy_Bird/
Flip_Flop/
Full_Adder/
Multiplexer/
Reflex_Game/
Turkey_Counter/
# Logic Design Projects - Verilog Code
Welcome to my repository containing Verilog (.v) source files for various projects completed during my Introduction to Logic Design. These projects were originally developed using Vivado and programmed onto a Basys 3 FPGA board.
## About This Repository
This repository is dedicated to showcasing my Verilog coding skills and the practical applications of these skills in digital logic design. The focus is on the Verilog code itself, therefore, only the .v files are included here. Each project demonstrates different aspects of digital logic design, ranging from basic logic gates to more complex digital systems.
## Getting Started
Prerequisites
- Xilinx Vivado (for code compilation and simulation)
- Basys 3 FPGA Board (for implementation, not required for code review)
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