Single-Cycle-RISC-V-Processor
所属分类：处理器开发
开发工具：SystemVerilog
文件大小：0KB
下载次数：0
上传日期：2024-01-19 19:25:01
上 传 者：
sh-1993
说明： 我的RV32I处理器的实现基于教材-数字设计和计算机架构：RISC-V版的莎拉哈里斯…
(My implementation of the RV32I processor based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris…)
文件列表:
rtl/
sim/
processor.png
riscvtest.mem
# Single Cycle RISC-V Processor
My implementation of the RV32IM processor based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris and David Harris
Microarchitecture:
The processor implements all base integer instructions except for ecall and ebreak. The 'riscvtest.mem' file contains the machine code for the processor to execute. Upon successful execution, the processor stores the value 25 in address 100 of data memory. The testbenches for each module in the design are also available.
近期下载者：
相关文件：
收藏者：