FPGA-Programming
所属分类：土木工程
开发工具：TeX
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上传日期：2024-02-13 08:58:38
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sh-1993
说明： 微型项目，“使用Verilog HDL的FPGA架构和编程”实验室研讨会，NIELIT，Calicut
(Mini project, Lab Workshop on "FPGA Architecture and Programming using Verilog HDL", NIELIT, Calicut)
文件列表:
project_1.cache/wt/
project_1.hw/
project_1.runs/
project_1.sim/sim_1/behav/xsim/
project_1.srcs/
Exp-No-33-Mini Project.pdf
Mini-project.pdf
project_1.xpr
vivado.jou
vivado.log
# FPGA-Programming
Mini project, Lab Workshop on "FPGA Architecture and Programming using Verilog HDL", NIELIT, Calicut
Code the above design in verilog HDL and implement the same on the FPGA
Kit allotted to you
Use Virtual input and Output IP Core for giving input I3, I2, I1, I0
CLK from the Kit.
Y3 Y2 Y1 Y0 need to be displayed on Chipscope IP Core.
1. 4-1 Mux use dataflow
2. Decoder use behaviour modeling
3. Latch use behaviour modeling
4. Counter- Use Xilinx IP Core.
5. Connect everything as miniproject.v and implement on the Kit
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