UART_IF
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：150KB
下载次数：3
上传日期：2011-11-24 15:47:03
上 传 者：
programmer01
说明： 该源代码实现通用串行接口接收发送。把串行接口的数据转换成总线数据流。便于进一步对数据处理。
(The source code achieve universal serial interface receive and send. The serial interface of data transfer into bus data flow. Facilitate further on data processing.)
文件列表:
UART_IF\disaddr.bsf (2755, 2010-08-20)
UART_IF\disaddr.vhd (2117, 2011-11-17)
UART_IF\disaddr.vhd.bak (2000, 2011-11-16)
UART_IF\rd_wr_encd.bsf (2773, 2010-08-20)
UART_IF\rd_wr_encd.vhd (2772, 2011-11-24)
UART_IF\rd_wr_encd.vhd.bak (2843, 2011-11-24)
UART_IF\r_uart.bsf (2151, 2010-08-20)
UART_IF\r_uart.vhd (2389, 2011-11-24)
UART_IF\r_uart.vhd.bak (2340, 2011-11-16)
UART_IF\UART_IF.bdf (13842, 2011-11-17)
UART_IF\UART_IF_Top.bsf (2509, 2011-11-17)
UART_IF\uart_ram.bsf (4863, 2010-08-20)
UART_IF\uart_ram.inc (918, 2010-08-20)
UART_IF\uart_ram.qip (368, 2010-08-20)
UART_IF\uart_ram.vhd (9567, 2010-08-20)
UART_IF\uart_ram_wave0.jpg (105879, 2010-08-20)
UART_IF\uart_ram_wave1.jpg (143426, 2010-08-20)
UART_IF\uart_ram_waveforms.html (1879, 2010-08-20)
UART_IF (0, 2011-11-24)
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