Verification-of-DE1-SoC-FPGA
所属分类：硬件设计
开发工具：Verilog
文件大小：0KB
下载次数：0
上传日期：2024-03-09 11:31:29
上 传 者：
sh-1993
说明： DE1 SoC现场可编程门阵列（FPGA）的测试台，用于检测DEVCOM陆军研究实验室实施保护技术后系统性能的任何变化
(A testbench for the DE1-SoC Field Programmable Gate Array (FPGA) to detect any changes in performance of the system after implementation of protection technology by DEVCOM Army Research Lab)
文件列表:
final.qar
fpu_top.sof
fpu_top.v
memDump.tcl
mif_processor.py
With a team of 5 student engineers, developed a testbench for the DE1-SoC Field Programmable Gate Array (FPGA)
to detect any changes in performance of the system after implementation of protection technology by DEVCOM Army Research Lab
final.qar is the Quartus II archive for the program to be flashed to the DE1-SoC that will utilize a high percentage of board resources to stress the board.
fpu_top.sof is the compilation of final .qar and is ready to be flashed to the DE1-SoC to begin the testbench on the board.
memDump.tcl extracts the memory contents from the RAMs created in the final.qar and puts the data into .mif files
mif_processor.py then extracts the data in the mif files generated by memDump.tcl and inserts the data into .csv files. This is for the creation of graphs, tables
and other form of presentable media of the data to achieve the goal of comparing functional correctness of onboard FPUs pre board modification and post board modification.
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