PYGMY-V32I
说明： Pygmy是一种微型RISC-V可编程微控制器，用于完全用Verilog HDL设计的嵌入式FPGA应用
(Pygmy is a tiny RISC-V programmable microcontroller for embedded FPGA applications designed entirely in Verilog HDL)
(Pygmy is a tiny RISC-V programmable microcontroller for embedded FPGA applications designed entirely in Verilog HDL)
文件列表:
rtl/
sw/
Makefile
PYGMY.svg
arty.xdc
build.tcl
sw/
Makefile
PYGMY.svg
arty.xdc
build.tcl
# Pygmy
Pygmy is a tiny 2-stage pipelined RISC-V programmable **microcontroller** for embedded/FPGA applications designed entirely in Verilog HDL. Its initial use case is to replace complex state machines and to perform house-keeping operations in large systems that need a flexible master controller.
* Go to [sw] directory and hit make clean/make all.
* Got to [rtl] directory and hit make clean/make all.
* Load the bitstream generated using any program you prefer.
Available Features:
* Fully programmable in C.
* UART Debug using PUTTY.
* 256 Byte - ROM/RAM (expandable).
* Byte/Half-Word/Word addressable memory.
The project has be developed/verified for the artix-735t FPGA but it should be able to run in other platforms too.
This is an early version of what the final project is envisioned to be. Any incoming feature request is welcome.
TODO:
* Interrupt controller.
* Expandability (ability to include multiple peripherals).
* GPIO interface.
* Further reduce size in LUTs and FF.
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