CPLD_SPI
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1034KB
下载次数：65
上传日期：2011-11-26 16:23:18
上 传 者：
maoying3826
说明： 单片机通过SPI接口与FPGA进行通信的VHDL代码，程序实际可用的
(Microcontroller through the SPI interface to communicate with the FPGA, a very common)
文件列表:
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e\ModelSim_ tb_spi().pdf (231459, 2008-08-31)
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e\spi.v (4190, 2008-08-31)
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e.rar (110978, 2009-04-26)
CPLD_SPI\an485_CN.pdf (228304, 2009-04-26)
CPLD_SPI\an485_design_example\code\SPI_Master.v (5023, 2007-02-08)
CPLD_SPI\an485_design_example\modelsim\SPI_Master.cr.mti (1105, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\SPI_Master.mpf (10100, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\SPI_Master.v (5023, 2007-02-08)
CPLD_SPI\an485_design_example\modelsim\SPI_Master_test.v (10393, 2007-02-10)
CPLD_SPI\an485_design_example\modelsim\SPI_Master_test.v.bak (10393, 2007-02-08)
CPLD_SPI\an485_design_example\modelsim\transcript (2236, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\vsim.wlf (40960, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\wave.bmp (406614, 2007-02-10)
CPLD_SPI\an485_design_example\modelsim\wave.do (1440, 2007-02-10)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master\verilog.psm (34033, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master\_primary.dat (2997, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master\_primary.vhd (583, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test\verilog.psm (63144, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test\_primary.dat (7005, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test\_primary.vhd (90, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\_info (649, 2007-02-25)
CPLD_SPI\an485_design_example\quartus\db\prev_cmp_SPI_Master.asm.qmsg (2037, 2007-11-16)
CPLD_SPI\an485_design_example\quartus\db\prev_cmp_SPI_Master.fit.qmsg (48847, 2007-11-16)
CPLD_SPI\an485_design_example\quartus\db\prev_cmp_SPI_Master.map.qmsg (8839, 2007-11-16)
CPLD_SPI\an485_design_example\quartus\db\prev_cmp_SPI_Master.tan.qmsg (71582, 2007-11-16)
CPLD_SPI\an485_design_example\quartus\db\SPI_Master.db_info (136, 2001-01-19)
CPLD_SPI\an485_design_example\quartus\db\SPI_Master.eco.cdb (141, 2001-01-19)
CPLD_SPI\an485_design_example\quartus\db\SPI_Master.sld_design_entry.sci (134, 2001-01-19)
CPLD_SPI\an485_design_example\quartus\SPI_Master.asm.rpt (7640, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.done (26, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.dpf (239, 2007-02-25)
CPLD_SPI\an485_design_example\quartus\SPI_Master.fit.rpt (72737, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.fit.smsg (334, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.fit.summary (371, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.flow.rpt (5640, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.map.rpt (21276, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.map.smsg (218, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.map.summary (366, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.pin (15525, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.pof (7856, 2007-11-22)
... ...
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