xsp605_ilinx_mig_ipcore
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：8567KB
下载次数：19
上传日期：2011-11-28 18:53:02
上 传 者：
Fanrong
说明： 赛林思开发板sp605的内存管理单元的ip核调试通过
(SP605 IP core mig)
文件列表:
core_mig\coregen.cgc (2049, 2010-12-03)
core_mig\coregen.cgp (518, 2010-12-03)
core_mig\core_mig\core_mig.ucf (8739, 2010-12-03)
core_mig\core_mig\rtl\core_mig.v (20275, 2010-12-03)
core_mig\core_mig\rtl\iodrp_controller.v (11426, 2009-11-03)
core_mig\core_mig\rtl\iodrp_mcb_controller.v (15423, 2009-11-03)
core_mig\core_mig\rtl\mcb_raw_wrapper.v (259734, 2010-03-03)
core_mig\core_mig\rtl\mcb_soft_calibration.v (55041, 2010-03-13)
core_mig\core_mig\rtl\mcb_soft_calibration_top.v (11961, 2010-02-11)
core_mig\core_mig\rtl\memc3_infrastructure.v (10241, 2010-12-03)
core_mig\core_mig\rtl\memc3_wrapper.v (27752, 2010-12-03)
core_mig\core_mig\test_data.v (3696, 2010-12-03)
core_mig\core_mig\top.v (4372, 2010-12-03)
core_mig\core_mig.cmd_log (223, 2010-12-03)
core_mig\core_mig.gise (19245, 2010-12-08)
core_mig\core_mig.rar (64878, 2010-12-03)
core_mig\core_mig.tfi (1859, 2010-12-03)
core_mig\core_mig.ucf (8739, 2010-12-07)
core_mig\core_mig.xise (37932, 2010-12-08)
core_mig\core_mig_summary.html (3707, 2010-12-03)
core_mig\fuse.log (7268, 2010-12-08)
core_mig\ipcore_dir\core_mig\docs\ug388.pdf (1987289, 2009-11-03)
core_mig\ipcore_dir\core_mig\docs\ug416.pdf (4206757, 2010-03-04)
core_mig\ipcore_dir\core_mig\example_design\datasheet.txt (2613, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\log.txt (2934, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\mig.prj (3050, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\create_ise.bat (3142, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\example_top.ucf (9078, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\icon_coregen.xco (1372, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\ila_coregen.xco (3861, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\ise_flow.bat (3933, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\ise_run.txt (1215, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\makeproj.bat (28, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\mem_interface_top.ut (385, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\rem_files.bat (7949, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\set_ise_prop.tcl (5870, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\par\vio_coregen.xco (1560, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\rtl\example_top.v (22947, 2010-12-03)
core_mig\ipcore_dir\core_mig\example_design\rtl\iodrp_controller.v (11426, 2009-11-03)
... ...
The following files were generated for 'core_mig' in directory
D:\core_mig\ipcore_dir\
core_mig\docs\ug388.pdf:
Please see the core data sheet.
core_mig\docs\ug416.pdf:
Please see the core data sheet.
core_mig_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
core_mig\example_design\datasheet.txt:
Please see the core data sheet.
core_mig\example_design\log.txt:
Please see the core data sheet.
core_mig\example_design\mig.prj:
Please see the core data sheet.
core_mig\example_design\par\create_ise.bat:
Please see the core data sheet.
core_mig\example_design\par\example_top.ucf:
Please see the core data sheet.
core_mig\example_design\par\icon_coregen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig\example_design\par\ila_coregen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig\example_design\par\ise_flow.bat:
Please see the core data sheet.
core_mig\example_design\par\ise_run.txt:
Please see the core data sheet.
core_mig\example_design\par\makeproj.bat:
Please see the core data sheet.
core_mig\example_design\par\mem_interface_top.ut:
Please see the core data sheet.
core_mig\example_design\par\readme.txt:
Please see the core data sheet.
core_mig\example_design\par\rem_files.bat:
Please see the core data sheet.
core_mig\example_design\par\set_ise_prop.tcl:
Please see the core data sheet.
core_mig\example_design\par\vio_coregen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig\example_design\rtl\example_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\iodrp_controller.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\iodrp_mcb_controller.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\mcb_raw_wrapper.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\mcb_soft_calibration.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\mcb_soft_calibration_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\memc3_infrastructure.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\memc3_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\memc3_wrapper.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\afifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\cmd_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\cmd_prbs_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\data_prbs_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\init_mem_pattern_ctr.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\mcb_flow_control.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\mcb_traffic_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\pipeline_inserter.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\rd_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\read_data_path.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\read_posted_fifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\sp6_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\tg_status.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\v6_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\wr_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\rtl\traffic_gen\write_data_path.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\sim\functional\core_mig.prj:
Please see the core data sheet.
core_mig\example_design\sim\functional\ddr3_model_c3.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\sim\functional\ddr3_model_parameters_c3.vh:
Please see the core data sheet.
core_mig\example_design\sim\functional\glbl.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\sim\functional\isim.bat:
Please see the core data sheet.
core_mig\example_design\sim\functional\isim.tcl:
Please see the core data sheet.
core_mig\example_design\sim\functional\readme.txt:
Please see the core data sheet.
core_mig\example_design\sim\functional\sim.do:
Please see the core data sheet.
core_mig\example_design\sim\functional\sim_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\example_design\synth\example_top.lso:
Please see the core data sheet.
core_mig\example_design\synth\example_top.prj:
Please see the core data sheet.
core_mig\example_design\synth\mem_interface_top_synp.sdc:
Please see the core data sheet.
core_mig\example_design\synth\script_synp.tcl:
Please see the core data sheet.
core_mig\user_design\datasheet.txt:
Please see the core data sheet.
core_mig\user_design\log.txt:
Please see the core data sheet.
core_mig\user_design\mig.prj:
Please see the core data sheet.
core_mig\user_design\par\core_mig.ucf:
Please see the core data sheet.
core_mig\user_design\par\create_ise.bat:
Please see the core data sheet.
core_mig\user_design\par\icon_coregen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig\user_design\par\ila_coregen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig\user_design\par\ise_flow.bat:
Please see the core data sheet.
core_mig\user_design\par\ise_run.txt:
Please see the core data sheet.
core_mig\user_design\par\makeproj.bat:
Please see the core data sheet.
core_mig\user_design\par\mem_interface_top.ut:
Please see the core data sheet.
core_mig\user_design\par\readme.txt:
Please see the core data sheet.
core_mig\user_design\par\rem_files.bat:
Please see the core data sheet.
core_mig\user_design\par\set_ise_prop.tcl:
Please see the core data sheet.
core_mig\user_design\par\vio_coregen.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig\user_design\rtl\core_mig.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\iodrp_controller.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\iodrp_mcb_controller.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\mcb_raw_wrapper.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\mcb_soft_calibration.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\mcb_soft_calibration_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\memc3_infrastructure.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\rtl\memc3_wrapper.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\afifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\cmd_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\cmd_prbs_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\core_mig.prj:
Please see the core data sheet.
core_mig\user_design\sim\data_prbs_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\ddr3_model_c3.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\ddr3_model_parameters_c3.vh:
Please see the core data sheet.
core_mig\user_design\sim\glbl.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\init_mem_pattern_ctr.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\isim.bat:
Please see the core data sheet.
core_mig\user_design\sim\isim.tcl:
Please see the core data sheet.
core_mig\user_design\sim\mcb_flow_control.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\mcb_traffic_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\memc3_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\pipeline_inserter.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\rd_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\read_data_path.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\read_posted_fifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\readme.txt:
Please see the core data sheet.
core_mig\user_design\sim\sim.do:
Please see the core data sheet.
core_mig\user_design\sim\sim_tb_top.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\sp6_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\tg_status.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\v6_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\wr_data_gen.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\sim\write_data_path.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
core_mig\user_design\synth\core_mig.lso:
Please see the core data sheet.
core_mig\user_design\synth\core_mig.prj:
Please see the core data sheet.
core_mig\user_design\synth\mem_interface_top_synp.sdc:
Please see the core data sheet.
core_mig\user_design\synth\script_synp.tcl:
Please see the core data sheet.
core_mig.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
core_mig.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
core_mig.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
core_mig.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
core_mig_readme.txt:
Text file indicating the files generated and how they are used.
core_mig_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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