sdram_vhdl
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：871KB
下载次数：4
上传日期：2011-12-02 14:36:29
上 传 者：
xuepengzhan
说明： DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。
(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good. )
文件列表:
sdram_vhdl (0, 2011-12-02)
sdram_vhdl\sdram_doc (0, 2000-06-02)
sdram_vhdl\sdram_doc\ddr_sdram.pdf (472801, 2000-05-30)
sdram_vhdl\sdram_r (0, 2000-05-23)
sdram_vhdl\sdram_r\mt46v4m16.v (44955, 2000-03-29)
sdram_vhdl\sdram_route (0, 2000-06-02)
sdram_vhdl\sdram_route\ddr_sdram.csf (10358, 2000-06-02)
sdram_vhdl\sdram_route\ddr_sdram.esf (618, 2000-06-02)
sdram_vhdl\sdram_route\ddr_sdram.psf (2443, 2000-06-02)
sdram_vhdl\sdram_route\ddr_sdram.quartus (194, 2000-06-02)
sdram_vhdl\sdram_route\ddr_sdram.vqm (595323, 2000-05-22)
sdram_vhdl\sdram_route\pll1.v (4648, 2000-05-20)
sdram_vhdl\sdram_simulation (0, 2000-06-02)
sdram_vhdl\sdram_simulation\ddr_compile_all.v (213, 2000-05-20)
sdram_vhdl\sdram_simulation\ddr_sdram_tb.v (18362, 2000-05-19)
sdram_vhdl\sdram_simulation\modelsim.ini (7728, 2000-05-21)
sdram_vhdl\sdram_simulation\work (0, 2000-05-23)
sdram_vhdl\sdram_simulation\work\altclklock (0, 2000-05-23)
sdram_vhdl\sdram_simulation\work\altclklock\verilog.psm (20672, 2000-05-21)
sdram_vhdl\sdram_simulation\work\altclklock\_primary.dat (2333, 2000-05-21)
sdram_vhdl\sdram_simulation\work\altclklock\_primary.vhd (899, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_command (0, 2000-05-23)
sdram_vhdl\sdram_simulation\work\ddr_command\verilog.psm (46232, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_command\_primary.dat (5126, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_command\_primary.vhd (1327, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_control_interface (0, 2000-05-23)
sdram_vhdl\sdram_simulation\work\ddr_control_interface\verilog.psm (21720, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_control_interface\_primary.dat (2785, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_control_interface\_primary.vhd (1113, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_data_path (0, 2000-05-23)
sdram_vhdl\sdram_simulation\work\ddr_data_path\verilog.psm (24088, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_data_path\_primary.dat (3215, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_data_path\_primary.vhd (817, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_sdram (0, 2000-05-23)
sdram_vhdl\sdram_simulation\work\ddr_sdram\verilog.psm (28640, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_sdram\_primary.dat (4552, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_sdram\_primary.vhd (1085, 2000-05-21)
sdram_vhdl\sdram_simulation\work\ddr_sdram_tb (0, 2000-05-23)
... ...
File/Directory Description
=============================================================================
\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
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